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    • 5. 发明授权
    • Method for automatically modifying integrated circuit layout
    • 自动修改集成电路布局的方法
    • US07496862B2
    • 2009-02-24
    • US11512823
    • 2006-08-29
    • Mi-Chang ChangSu-Ya LinJen-Hang YangLi-Chun Tien
    • Mi-Chang ChangSu-Ya LinJen-Hang YangLi-Chun Tien
    • G06F17/50
    • G06F17/5068H01L27/0207H01L27/11807
    • This invention discloses a method for automatically adjusting cell layout height and transistor width of one type of MOS IC cells, the method comprising following steps of Boolean logic operations on at least one such cell: identifying one or more MOS transistor active areas (ODs) and one or more power ODs in an OD layer, expanding the MOS transistor ODs in a predetermined direction by a first predetermined amount, shifting the power ODs in the predetermined direction by a second predetermined amount, expanding one or more MOS transistor gate areas in the predetermined direction by a third predetermined amount, shifting one or more power OD contacts in the predetermined direction by approximately the second predetermined amount, and stretching one or more metal areas (M1s) in a metal layer that is directly coupled to the OD layer through contacts electronically, in the predetermined direction by a predetermined way.
    • 本发明公开了一种用于自动调整一个类型的MOS IC单元的单元布局高度和晶体管宽度的方法,所述方法包括以下步骤:对至少一个这样的单元进行布尔逻辑运算:识别一个或多个MOS晶体管有源区(OD)和 在OD层中的一个或多个功率OD,将预定方向上的MOS晶体管OD扩展第一预定量,将预定方向上的功率OD移动第二预定量,将预定的一个或多个MOS晶体管栅极区域扩展 方向移动第三预定量,将一个或多个功率OD触点沿预定方向移动大约第二预定量,以及通过电子接触在一个金属层中直接连接到OD层的金属层中拉伸一个或多个金属区域(M1) ,以预定的方式在预定方向上。
    • 6. 发明申请
    • Method for automatically modifying integrated circuit layout
    • 自动修改集成电路布局的方法
    • US20080059916A1
    • 2008-03-06
    • US11512823
    • 2006-08-29
    • Mi-Chang ChangSu-Ya LinJen-Hang YangLi-Chun Tien
    • Mi-Chang ChangSu-Ya LinJen-Hang YangLi-Chun Tien
    • G06F17/50
    • G06F17/5068H01L27/0207H01L27/11807
    • This invention discloses a method for automatically adjusting cell layout height and transistor width of one type of MOS IC cells, the method comprising following steps of Boolean logic operations on at least one such cell: identifying one or more MOS transistor active areas (ODs) and one or more power ODs in an OD layer, expanding the MOS transistor ODs in a predetermined direction by a first predetermined amount, shifting the power ODs in the predetermined direction by a second predetermined amount, expanding one or more MOS transistor gate areas in the predetermined direction by a third predetermined amount, shifting one or more power OD contacts in the predetermined direction by approximately the second predetermined amount, and stretching one or more metal areas (M1s) in a metal layer that is directly coupled to the OD layer through contacts electronically, in the predetermined direction by a predetermined way.
    • 本发明公开了一种用于自动调整一个类型的MOS IC单元的单元布局高度和晶体管宽度的方法,所述方法包括以下步骤:对至少一个这样的单元进行布尔逻辑运算:识别一个或多个MOS晶体管有源区(OD)和 在OD层中的一个或多个功率OD,将预定方向上的MOS晶体管OD扩展第一预定量,将预定方向上的功率OD移动第二预定量,将预定的一个或多个MOS晶体管栅极区域扩展 方向移动第三预定量,将一个或多个功率OD触点沿预定方向移动大约第二预定量,以及通过电子接触在一个金属层中直接连接到OD层的金属层中拉伸一个或多个金属区域(M1) ,以预定的方式在预定方向上。