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1. 发明授权

US07427876B1 Reversible sequential element and reversible sequential circuit thereof 有权
标题翻译：可逆顺序元件及其可逆顺序电路
公开(公告)号：US07427876B1
公开(公告)日：2008-09-23
申请号：US11687983
申请日：2007-03-19
申请人： Chun Yao Wang , Min Lun Chuang
发明人： Chun Yao Wang , Min Lun Chuang
IPC分类号： H03K19/173
CPC分类号： H03K3/0372
摘要： A reversible sequential element comprises a first logic gate and a second logic gate. The first logic gate includes a first input terminal, a second input terminal, a third input terminal, a first output terminal coupled to the first input terminal, a second output terminal and a third output terminal. The second logic gate includes a first input line, a second input line, a first output line and a second output line. When the first input terminal is set to a first state, the second input terminal is coupled to the third output terminal and the third input terminal is coupled to the second output terminal; otherwise, the second input terminal is coupled to the second output terminal and the third input terminal is coupled to the third output terminal. The third output terminal, second input line and second output line are coupled to each other. The input signal carried on the first input line is set as 0 so that the second output line and the first output line have the same output.
摘要翻译：可逆顺序元件包括第一逻辑门和第二逻辑门。第一逻辑门包括第一输入端，第二输入端，第三输入端，耦合到第一输入端的第一输出端，第二输出端和第三输出端。第二逻辑门包括第一输入线，第二输入线，第一输出线和第二输出线。当第一输入端子被设置为第一状态时，第二输入端子耦合到第三输出端子，第三输入端子耦合到第二输出端子; 否则，第二输入端子耦合到第二输出端子，第三输入端子耦合到第三输出端子。第三输出端子，第二输入线和第二输出线彼此耦合。将第一输入线上承载的输入信号设置为0，使得第二输出线和第一输出线具有相同的输出。

2. 发明授权

US07432738B1 Reversible sequential apparatuses 有权
标题翻译：可逆顺序设备
公开(公告)号：US07432738B1
公开(公告)日：2008-10-07
申请号：US11692394
申请日：2007-03-28
申请人： Chun Yao Wang , Min Lun Chuang
发明人： Chun Yao Wang , Min Lun Chuang
IPC分类号： H03K19/173
CPC分类号： H03K3/037
摘要： A reversible sequential apparatus comprises a first logic gate and a second logic gate. The first logic gate includes first, second and third input terminals and first, second and third output terminals. The second logic gate includes first and second input lines and first and second output lines. The first input terminal for carrying a clock signal is coupled to the first output terminal and the second input terminal for carrying an input signal is coupled to the second output terminal. When the first input terminal and the second input terminal are simultaneously set to a first state, the level of the third output terminal is inverse to the level of the third input terminal; otherwise, the level of the third output terminal is identical to the level of the third input terminal. The third output terminal, second input line and second output line are coupled to each other. The input signal carried on the first input line is set to a constant level so that the second output line and the first output line have the same outputs.
摘要翻译：可逆顺序设备包括第一逻辑门和第二逻辑门。第一逻辑门包括第一，第二和第三输入端以及第一，第二和第三输出端。第二逻辑门包括第一和第二输入线以及第一和第二输出线。用于承载时钟信号的第一输入端耦合到第一输出端，并且用于承载输入信号的第二输入端耦合到第二输出端。当第一输入端子和第二输入端子同时被设置为第一状态时，第三输出端子的电平与第三输入端子的电平相反; 否则，第三输出端子的电平与第三输入端子的电平相同。第三输出端子，第二输入线和第二输出线彼此耦合。将第一输入线上承载的输入信号设定为恒定电平，使得第二输出线和第一输出线具有相同的输出。

3. 发明申请

US20080238480A1 REVERSIBLE SEQUENTIAL APPARATUSES 有权
标题翻译：可逆序列设备
公开(公告)号：US20080238480A1
公开(公告)日：2008-10-02
申请号：US11692394
申请日：2007-03-28
申请人： Chun Yao Wang , Min Lun Chuang
发明人： Chun Yao Wang , Min Lun Chuang
IPC分类号： H03K19/173
CPC分类号： H03K3/037
摘要： A reversible sequential apparatus comprises a first logic gate and a second logic gate. The first logic gate includes first, second and third input terminals and first, second and third output terminals. The second logic gate includes first and second input lines and first and second output lines. The first input terminal for carrying a clock signal is coupled to the first output terminal and the second input terminal for carrying an input signal is coupled to the second output terminal. When the first input terminal and the second input terminal are simultaneously set to a first state, the level of the third output terminal is inverse to the level of the third input terminal; otherwise, the level of the third output terminal is identical to the level of the third input terminal. The third output terminal, second input line and second output line are coupled to each other. The input signal carried on the first input line is set to a constant level so that the second output line and the first output line have the same outputs.
摘要翻译：可逆顺序设备包括第一逻辑门和第二逻辑门。第一逻辑门包括第一，第二和第三输入端以及第一，第二和第三输出端。第二逻辑门包括第一和第二输入线以及第一和第二输出线。用于承载时钟信号的第一输入端耦合到第一输出端，并且用于承载输入信号的第二输入端耦合到第二输出端。当第一输入端子和第二输入端子同时被设置为第一状态时，第三输出端子的电平与第三输入端子的电平相反; 否则，第三输出端子的电平与第三输入端子的电平相同。第三输出端子，第二输入线和第二输出线彼此耦合。将第一输入线上承载的输入信号设定为恒定电平，使得第二输出线和第一输出线具有相同的输出。

4. 发明申请

US20080238479A1 REVERSIBLE SEQUENTIAL ELEMENT AND REVERSIBLE SEQUENTIAL CIRCUIT THEREOF 有权
标题翻译：可逆序列元素及其可逆序列电路
公开(公告)号：US20080238479A1
公开(公告)日：2008-10-02
申请号：US11687983
申请日：2007-03-19
申请人： Chun Yao Wang , Min Lun Chuang
发明人： Chun Yao Wang , Min Lun Chuang
IPC分类号： H03K19/173
CPC分类号： H03K3/0372
摘要： A reversible sequential element comprises a first logic gate and a second logic gate. The first logic gate includes a first input terminal, a second input terminal, a third input terminal, a first output terminal coupled to the first input terminal, a second output terminal and a third output terminal. The second logic gate includes a first input line, a second input line, a first output line and a second output line. When the first input terminal is set to a first state, the second input terminal is coupled to the third output terminal and the third input terminal is coupled to the second output terminal; otherwise, the second input terminal is coupled to the second output terminal and the third input terminal is coupled to the third output terminal. The third output terminal, second input line and second output line are coupled to each other. The input signal carried on the first input line is set as 0 so that the second output line and the first output line have the same output.
摘要翻译：可逆顺序元件包括第一逻辑门和第二逻辑门。第一逻辑门包括第一输入端，第二输入端，第三输入端，耦合到第一输入端的第一输出端，第二输出端和第三输出端。第二逻辑门包括第一输入线，第二输入线，第一输出线和第二输出线。当第一输入端子被设置为第一状态时，第二输入端子耦合到第三输出端子，第三输入端子耦合到第二输出端子; 否则，第二输入端子耦合到第二输出端子，第三输入端子耦合到第三输出端子。第三输出端子，第二输入线和第二输出线彼此耦合。将第一输入线上承载的输入信号设置为0，使得第二输出线和第一输出线具有相同的输出。

5. 发明申请

US20090191686A1 Method for Preparing Doped Polysilicon Conductor and Method for Preparing Trench Capacitor Structure Using the Same 审中-公开
标题翻译：掺杂多晶硅导体的制备方法及使用其制备沟槽电容器结构的方法
公开(公告)号：US20090191686A1
公开(公告)日：2009-07-30
申请号：US12108330
申请日：2008-04-23
申请人： Chun Yao Wang , Fu Hsiung Yang
发明人： Chun Yao Wang , Fu Hsiung Yang
IPC分类号： H01L21/02 , H01L21/3215
CPC分类号： H01L21/32155 , H01L27/1087 , H01L28/84 , H01L29/66181
摘要： A method for preparing a doped polysilicon conductor according to this aspect of the present invention comprises the steps of (a) placing a substrate in a reaction chamber, (b) performing a deposition process to form a polysilicon layer on the substrate, (c) performing a grain growth process to form a plurality of polysilicon grains on the polysilicon layer, and (d) performing a dopant diffusion process to diffuse conductive dopants into the polysilicon layer via the polysilicon grains to form the doped polysilicon conductor.
摘要翻译：根据本发明的这个方面的制备掺杂多晶硅导体的方法包括以下步骤：（a）将衬底放置在反应室中，（b）进行沉积工艺以在衬底上形成多晶硅层，（c）进行晶粒生长处理以在所述多晶硅层上形成多个多晶硅晶粒，以及（d）进行掺杂剂扩散处理，以通过所述多晶硅晶粒将导电掺杂剂扩散到所述多晶硅层中，以形成所述掺杂多晶硅导体。

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