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1. 发明授权

US06812149B1 Method of forming junction isolation to isolate active elements 有权
标题翻译：形成结隔离以隔离有源元件的方法
公开(公告)号：US06812149B1
公开(公告)日：2004-11-02
申请号：US10662381
申请日：2003-09-16
申请人： Chun Chi Wang , Chun Lien Su , Wen Pin Lu
发明人： Chun Chi Wang , Chun Lien Su , Wen Pin Lu
IPC分类号： H01L21311
CPC分类号： H01L21/761
摘要： A method of forming junction isolation to isolate active elements. A substrate having a plurality of active areas and an isolation area between active areas is provided. A first gate structure is formed on part of the substrate located in the active areas and, simultaneously, a second gate structure serving as a dummy gate structure is formed on the substrate located in the isolation area. A first doped region is formed in the substrate located at two sides of the first and the second gate structures. A bottom anti-reflection layer is formed on the substrate, the first gate structure and the second gate structure. Part of the bottom anti-reflection layer is etched to expose the second gate structure. The second gate structure is removed to expose the substrate. A second doped region serving as a junction isolation region is formed in the substrate located in the isolation area.
摘要翻译：形成结隔离以隔离有源元件的方法。提供了具有多个有源区域和有源区域之间的隔离区域的衬底。第一栅极结构形成在位于有源区域中的衬底的一部分上，并且同时，在位于隔离区域中的衬底上形成用作虚设栅极结构的第二栅极结构。在位于第一和第二栅极结构的两侧的衬底中形成第一掺杂区域。在基板，第一栅极结构和第二栅极结构上形成底部防反射层。底部抗反射层的一部分被蚀刻以暴露第二栅极结构。去除第二栅极结构以暴露衬底。在位于隔离区域的基板中形成用作结隔离区域的第二掺杂区域。

2. 发明授权

US07596028B2 Variable program and program verification methods for a virtual ground memory in easing buried drain contacts 有权
标题翻译：用于虚拟接地存储器的可变程序和程序验证方法，以缓解埋地漏接点
公开(公告)号：US07596028B2
公开(公告)日：2009-09-29
申请号：US11617007
申请日：2006-12-28
申请人： Ming Shiang Chen , Wen Pin Lu , I-Jen Huang , Chi Yuan Chin , Nian-Kai Zous
发明人： Ming Shiang Chen , Wen Pin Lu , I-Jen Huang , Chi Yuan Chin , Nian-Kai Zous
IPC分类号： G11C11/34
CPC分类号： G11C16/10 , G11C16/3454 , G11C16/3459
摘要： Methods for programming and program verification of a flash memory are described that ease the buried drain contact induced operation and increase the retention window. In a first aspect of the invention, a program operation method provides varying program biases which are applied to different groups of memory cells. The program biases can be supplied as drain bias voltages or gate bias voltages. The program biases vary depending on which group of memory cells is programmed. In one embodiment, a first drain voltage VD1 is applied to the first group of memory cells M0 and Mn. A second drain voltage VD2 is applied to the second group of memory cells M1 and Mn-1, where VD2=VD1+ΔVD. In a second aspect of the invention, a plurality of program verification voltage levels are selected to verify that the memory cells pass the program voltage levels.
摘要翻译：描述了用于快速存储器的编程和程序验证的方法，其易于埋入漏极接触引起的操作并增加保持窗口。在本发明的第一方面，一种程序操作方法提供了应用于不同组的存储单元的变化的程序偏移。程序偏置可以作为漏极偏置电压或栅极偏置电压提供。程序偏移根据编程的哪组存储单元而有所不同。在一个实施例中，将第一漏极电压VD1施加到第一组存储器单元M0和Mn。第二漏极电压VD2被施加到第二组存储器单元M1和Mn-1，其中VD2 = VD1 + DeltaVD。在本发明的第二方面中，选择多个程序验证电压电平以验证存储单元是否通过编程电压电平。

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