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    • 7. 发明授权
    • Method of forming gate electrode in semiconductor device
    • 在半导体器件中形成栅电极的方法
    • US6165884A
    • 2000-12-26
    • US457162
    • 1999-12-08
    • Sang Moo LeeHyeon Soo KimIn Seok Yeo
    • Sang Moo LeeHyeon Soo KimIn Seok Yeo
    • H01L29/78H01L21/28H01L21/336H01L21/3205
    • H01L21/28052
    • A method of forming a gate electrode in a semiconductor device which can easily perform etching process for forming the gate electrode and reduce the resistivity of a gate electrode, is disclosed. In the present invention, a gate oxide layer, an amorphous silicon layer and a tungsten silicide layer are sequentially formed on a semiconductor substrate. A mask oxide pattern is then formed on the tungsten silicide layer in the shape of a gate electrode. Next, the tungsten silicide layer and the amorphous silicon layer are etched using the mask oxide pattern as an etch mask, to form a gate electrode. Thereafter, the amorphous silicon layer and the tungsten silicide layer of the gate electrode are thermal-treated by RTP spike annealing and an oxide layer is then formed on the side wall of the gate electrode. According to the present invention, by reducing resistivity of a tungsten silicide layer, it is possible to apply a conventional gate electrode material to high integration device over 1GDRAM, thereby lowering cost to develop a new gate electrode material. Furthermore, etching process for forming a gate electrode is easily performed when using the tungsten silicide layer as the gate electrode material, thereby obtaining uniform gate electrode. As a result, the reliability of a device is improved.
    • 公开了一种在半导体器件中形成栅电极的方法,其可以容易地进行用于形成栅电极的蚀刻工艺并降低栅电极的电阻率。 在本发明中,在半导体衬底上依次形成栅极氧化层,非晶硅层和硅化钨层。 然后在栅电极形状的硅化钨层上形成掩模氧化物图案。 接下来,使用掩模氧化物图案作为蚀刻掩模来蚀刻硅化钨层和非晶硅层,以形成栅电极。 此后,通过RTP尖峰退火对栅电极的非晶硅层和硅化钨层进行热处理,然后在栅电极的侧壁上形成氧化物层。 根据本发明,通过降低硅化钨层的电阻率,可以将传统的栅极电极材料应用于超过1GDRAM的高集成度器件,从而降低开发新的栅电极材料的成本。 此外,当使用硅化钨层作为栅电极材料时,容易进行用于形成栅电极的蚀刻工艺,从而获得均匀的栅电极。 结果,提高了设备​​的可靠性。