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1. 发明申请

US20120291859A1 Multi-Junction Semiconductor Photovoltaic Apparatus and Methods 审中-公开
标题翻译：多结半导体光伏器件与方法
公开(公告)号：US20120291859A1
公开(公告)日：2012-11-22
申请号：US13109767
申请日：2011-05-17
申请人： Christopher Vineis , Martin U. Pralle , James E. Carey
发明人： Christopher Vineis , Martin U. Pralle , James E. Carey
IPC分类号： H01L31/06 , H01L31/18
CPC分类号： H01L31/076 , H01L31/02363 , H01L31/1804 , H01L31/1864 , H01L31/206 , Y02E10/547 , Y02E10/548 , Y02P70/521
摘要： A photovoltaic device and methods of manufacturing a photovoltaic device are disclosed. A photovoltaic device includes a first photovoltaic cell, a second photovoltaic cell, a semiconductor layer, and a doped layer. The second photovoltaic cell is in electrical communication with the first photovoltaic cell. The semiconductor layer includes a textured portion. The doped layer is configured to create a back surface field, the doped layer disposed between a proximal layer of the second photovoltaic cell and the semiconductor layer.
摘要翻译：公开了光伏器件和制造光伏器件的方法。光伏器件包括第一光伏电池，第二光伏电池，半导体层和掺杂层。第二光伏电池与第一光伏电池电连通。半导体层包括纹理部分。掺杂层被配置为产生背面场，所述掺杂层设置在第二光伏电池的近端层和半导体层之间。

2. 发明申请

US20140027774A1 Laser Processed Photovoltaic Devices and Associated Methods 审中-公开
标题翻译：激光加工光伏器件及相关方法
公开(公告)号：US20140027774A1
公开(公告)日：2014-01-30
申请号：US13472075
申请日：2012-05-15
申请人： Xia Li , Christopher Vineis , Martin U. Pralle
发明人： Xia Li , Christopher Vineis , Martin U. Pralle
IPC分类号： H01L31/105
CPC分类号： H01L31/1055 , H01L31/02363 , H01L31/0747 , Y02E10/50
摘要： Photovoltaic heterojunction devices, combination hetero- homo-junction devices, and associated methods are provided. In one aspect, for example, a photovoltaic device can include a doped semiconductor substrate having a first textured region and a second textured region opposite the first textured region, a first intrinsic semiconductor layer coupled to the first textured region opposite the semiconductor substrate and a second intrinsic semiconductor layer coupled to the second textured region opposite the semiconductor substrate. A first semiconductor layer can be coupled to the first intrinsic semiconductor layer opposite the first textured region, where the first semiconductor layer is doped to an opposite polarity of the doped semiconductor substrate. A second semiconductor layer can be coupled to the second intrinsic semiconductor layer opposite the second textured region, where the second semiconductor layer is doped to a same polarity as the semiconductor substrate but having a higher dopant concentration as the semiconductor substrate.
摘要翻译：提供了光伏异质结器件，组合异质结器件和相关方法。在一个方面，例如，光伏器件可以包括具有第一纹理区域和与第一纹理化区域相对的第二纹理化区域的掺杂半导体衬底，耦合到与半导体衬底相对的第一纹理化区域的第一本征半导体层，本征半导体层耦合到与半导体衬底相对的第二纹理区域。第一半导体层可以耦合到与第一纹理化区域相对的第一本征半导体层，其中第一半导体层被掺杂到掺杂半导体衬底的相反极性。第二半导体层可以耦合到与第二纹理化区域相对的第二本征半导体层，其中第二半导体层被掺杂到与半导体衬底相同的极性，但是具有较高的掺杂剂浓度作为半导体衬底。

3. 发明申请

US20060009012A1 Methods of fabricating semiconductor heterostructures 有权
标题翻译：制造半导体异质结构的方法
公开(公告)号：US20060009012A1
公开(公告)日：2006-01-12
申请号：US11227770
申请日：2005-09-15
申请人： Christopher Leitz , Christopher Vineis , Richard Westhoff , Vicky Yang , Matthew Currie
发明人： Christopher Leitz , Christopher Vineis , Richard Westhoff , Vicky Yang , Matthew Currie
IPC分类号： H01L21/20
CPC分类号： H01L21/0251 , C30B23/025 , C30B23/066 , C30B25/02 , C30B25/183 , C30B29/52 , H01L21/02381 , H01L21/0245 , H01L21/02505 , H01L21/02532 , H01L21/0262 , H01L21/823807
摘要： Dislocation pile-ups in compositionally graded semiconductor layers are reduced or eliminated, thereby leading to increased semiconductor device yield and manufacturability. This is accomplished by introducing a semiconductor layer having a plurality of threading dislocations distributed substantially uniformly across its surface as a starting layer and/or at least one intermediate layer during growth and relaxation of the compositionally graded layer. The semiconductor layer may include a seed layer disposed proximal to the surface of the semiconductor layer and having the threading dislocations uniformly distributed therein.
摘要翻译：组分梯度半导体层中的位错堆叠被减少或消除，从而导致半导体器件的产量和可制造性的提高。这是通过在组成渐变层的生长和弛豫期间引入具有多个穿透位错基本上均匀分布在其表面上的半导体层作为起始层和/或至少一个中间层来实现的。半导体层可以包括接近半导体层的表面并且穿透位错均匀分布在其中的晶种层。

4. 发明授权

US08698272B2 Semiconductor devices having reduced substrate damage and associated methods 有权
标题翻译：半导体器件具有降低的衬底损伤和相关方法
公开(公告)号：US08698272B2
公开(公告)日：2014-04-15
申请号：US13333482
申请日：2011-12-21
申请人： Christopher Vineis , James Carey , Xia Li
发明人： Christopher Vineis , James Carey , Xia Li
IPC分类号： H01L31/06
CPC分类号： H01L31/02363 , H01L31/03529 , H01L31/103 , H01L31/1032 , H01L31/1035 , Y02E10/50
摘要： Optoelectronic devices, materials, and associated methods having increased operating performance are provided. In one aspect, for example, an optoelectronic device can include a semiconductor material, a first doped region in the semiconductor material, a second doped region in the semiconductor material forming a junction with the first doped region, and a laser processed region associated with the junction. The laser processed region is positioned to interact with electromagnetic radiation. Additionally, at least a portion of a region of laser damage from the laser processed region has been removed such that the optoelectronic device has an open circuit voltage of from about 500 mV to about 800 mV.
摘要翻译：提供了具有增加的操作性能的光电器件，材料和相关方法。在一个方面，例如，光电子器件可以包括半导体材料，半导体材料中的第一掺杂区域，形成与第一掺杂区域的结的半导体材料中的第二掺杂区域和与第一掺杂区域相关联的激光处理区域交界处激光处理区域定位成与电磁辐射相互作用。此外，已经去除了来自激光加工区域的激光损伤区域的至少一部分，使得光电子器件具有约500mV至约800mV的开路电压。

5. 发明申请

US20120111396A1 Photovoltaic Devices and Associated Methods 审中-公开
标题翻译：光伏器件及相关方法
公开(公告)号：US20120111396A1
公开(公告)日：2012-05-10
申请号：US13101072
申请日：2011-05-04
申请人： Stephen D. Saylor , Jason Sickler , James Carey , Christopher Vineis , Xia Li
发明人： Stephen D. Saylor , Jason Sickler , James Carey , Christopher Vineis , Xia Li
IPC分类号： H01L31/0352 , H01L31/18
CPC分类号： H01L31/02363 , H01L31/068 , H01L31/1804 , Y02E10/547 , Y02P70/521
摘要： A method for making a semiconductor device includes providing a semiconductor material and doping at least a portion of the semiconductor material to form at least one doped region. A portion of the semiconductor material is removed with a pulsed laser from at least one first region to form at least one adjacent second region.
摘要翻译：制造半导体器件的方法包括提供半导体材料并掺杂半导体材料的至少一部分以形成至少一个掺杂区域。用来自至少一个第一区域的脉冲激光去除半导体材料的一部分，以形成至少一个相邻的第二区域。

6. 发明申请

US20060174818A1 Method of producing high quality relaxed silicon germanium layers 有权
公开(公告)号：US20060174818A1
公开(公告)日：2006-08-10
申请号：US11371442
申请日：2006-03-09
申请人： Eugene Fitzgerald , Richard Westhoff , Matthew Currie , Christopher Vineis , Thomas Langdo
发明人： Eugene Fitzgerald , Richard Westhoff , Matthew Currie , Christopher Vineis , Thomas Langdo
IPC分类号： C30B1/00 , C30B28/02 , C30B3/00 , C30B5/00
CPC分类号： C30B29/52 , C23C16/029 , C23C16/22 , C23C16/4401 , C30B25/02 , H01L21/0245 , H01L21/0251 , H01L21/02532 , H01L21/0262
摘要： A method for minimizing particle generation during deposition of a graded Si1-xGex layer on a semiconductor material includes providing a substrate in an atmosphere including a Si precursor and a Ge precursor, wherein the Ge precursor has a decomposition temperature greater than germane, and depositing the graded Si1-xGex layer having a final Ge content of greater than about 0.15 and a particle density of less than about 0.3 particles/cm2 on the substrate.

7. 发明授权

US07829442B2 Semiconductor heterostructures having reduced dislocation pile-ups and related methods 有权
标题翻译：具有减少位错堆积和相关方法的半导体异质结构
公开(公告)号：US07829442B2
公开(公告)日：2010-11-09
申请号：US11941629
申请日：2007-11-16
申请人： Richard Westhoff , Vicky K. Yang , Matthew T. Currie , Christopher Vineis , Christopher Leitz
发明人： Richard Westhoff , Vicky K. Yang , Matthew T. Currie , Christopher Vineis , Christopher Leitz
IPC分类号： H01L21/20
CPC分类号： H01L21/0251 , C30B23/025 , C30B23/066 , C30B25/02 , C30B25/183 , C30B29/52 , H01L21/02381 , H01L21/0245 , H01L21/02505 , H01L21/02532 , H01L21/0262 , H01L21/823807
摘要： Dislocation pile-ups in compositionally graded semiconductor layers are reduced or eliminated, thereby leading to increased semiconductor device yield and manufacturability. This is accomplished by introducing a semiconductor layer having a plurality of threading dislocations distributed substantially uniformly across its surface as a starting layer and/or at least one intermediate layer during growth and relaxation of the compositionally graded layer. The semiconductor layer may include a seed layer disposed proximal to the surface of the semiconductor layer and having the threading dislocations uniformly distributed therein.
摘要翻译：组分梯度半导体层中的位错堆叠被减少或消除，从而导致半导体器件的产量和可制造性的提高。这是通过在组成渐变层的生长和弛豫期间引入具有多个穿透位错基本上均匀分布在其表面上的半导体层作为起始层和/或至少一个中间层来实现的。半导体层可以包括接近半导体层的表面并且穿透位错均匀分布在其中的晶种层。

8. 发明授权

US07375385B2 Semiconductor heterostructures having reduced dislocation pile-ups 有权
标题翻译：具有减少位错堆积的半导体异质结构
公开(公告)号：US07375385B2
公开(公告)日：2008-05-20
申请号：US10646353
申请日：2003-08-22
申请人： Richard Westhoff , Vicky Yang , Matthew Currie , Christopher Vineis , Christopher Leitz
发明人： Richard Westhoff , Vicky Yang , Matthew Currie , Christopher Vineis , Christopher Leitz
IPC分类号： H01L35/26
CPC分类号： H01L21/0251 , C30B23/025 , C30B23/066 , C30B25/02 , C30B25/183 , C30B29/52 , H01L21/02381 , H01L21/0245 , H01L21/02505 , H01L21/02532 , H01L21/0262 , H01L21/823807
摘要： Dislocation pile-ups in compositionally graded semiconductor layers are reduced or eliminated, thereby leading to increased semiconductor device yield and manufacturability. This is accomplished by introducing a semiconductor layer having a plurality of threading dislocations distributed substantially uniformly across its surface as a starting layer and/or at least one intermediate layer during growth and relaxation of the compositionally graded layer. The semiconductor layer may include a seed layer disposed proximal to the surface of the semiconductor layer and having the threading dislocations uniformly distributed therein.
摘要翻译：组分梯度半导体层中的位错堆叠被减少或消除，从而导致半导体器件的产量和可制造性的提高。这是通过在组成渐变层的生长和弛豫期间引入具有多个穿透位错基本上均匀分布在其表面上的半导体层作为起始层和/或至少一个中间层来实现的。半导体层可以包括接近半导体层的表面并且穿透位错均匀分布在其中的晶种层。

9. 发明申请

US20120292729A1 Optoelectronic Devices Having Deep Level Defects and Associated Methods 审中-公开
标题翻译：具有深层缺陷和相关方法的光电器件
公开(公告)号：US20120292729A1
公开(公告)日：2012-11-22
申请号：US13472325
申请日：2012-05-15
申请人： Christopher Vineis
发明人： Christopher Vineis
IPC分类号： H01L31/0236 , H01L31/18
CPC分类号： H01L31/0236 , H01L31/02363 , H01L31/18 , Y02E10/50
摘要： Semiconductor structures, devices, and methods that can exhibit various enhanced properties, such as, for example, enhanced light detection properties are provided. In one aspect, for example, an optoelectronic device can include a semiconductor material having an enhanced absorption region and a first defect in the enhanced absorption region, where the first defect is a deep-level defect generated by a first defect carrier type that is either a deep-level donor carrier type or a deep-level acceptor carrier type. The device can also include a second defect in the enhanced absorption region, where the second defect is either a shallow-level defect or a deep-level defect, and where the second defect is generated by a second defect carrier type that is opposite to the first defect carrier type. Furthermore, the enhanced absorption region has an external quantum efficiency of at least about 0.5% for electromagnetic radiation wavelengths greater than 1250 nm.
摘要翻译：提供了能够呈现各种增强特性的半导体结构，器件和方法，例如增强的光检测性质。在一个方面，例如，光电子器件可以包括具有增强的吸收区域和增强的吸收区域中的第一缺陷的半导体材料，其中第一缺陷是由第一缺陷载体类型产生的深层缺陷，深层供体载体型或深层受体载体型。该装置还可以包括增强吸收区域中的第二缺陷，其中第二缺陷是浅层缺陷或深层缺陷，并且其中第二缺陷由与第二缺陷相反的第二缺陷载体类型产生第一缺陷载体类型。此外，增强的吸收区域对于大于1250nm的电磁辐射波长具有至少约0.5％的外部量子效率。

10. 发明申请

US20120104461A1 Semiconductor Heterostructures Having Reduced Dislocation Pile-Ups and Related Methods 有权
标题翻译：具有减少位错堆积和相关方法的半导体异质结构
公开(公告)号：US20120104461A1
公开(公告)日：2012-05-03
申请号：US13348778
申请日：2012-01-12
申请人： Christopher Leitz , Christopher Vineis , Richard Westhoff , Vicky Yang , Matthew Currie
发明人： Christopher Leitz , Christopher Vineis , Richard Westhoff , Vicky Yang , Matthew Currie
IPC分类号： H01L29/06 , H01L21/20
CPC分类号： H01L21/0251 , C30B23/025 , C30B23/066 , C30B25/02 , C30B25/183 , C30B29/52 , H01L21/02381 , H01L21/0245 , H01L21/02505 , H01L21/02532 , H01L21/0262 , H01L21/823807
摘要： Dislocation pile-ups in compositionally graded semiconductor layers are reduced or eliminated, thereby leading to increased semiconductor device yield and manufacturability. This is accomplished by introducing a semiconductor layer having a plurality of threading dislocations distributed substantially uniformly across its surface as a starting layer and/or at least one intermediate layer during growth and relaxation of the compositionally graded layer. The semiconductor layer may include a seed layer disposed proximal to the surface of the semiconductor layer and having the threading dislocations uniformly distributed therein.
摘要翻译：组分梯度半导体层中的位错堆叠被减少或消除，从而导致半导体器件的产量和可制造性的提高。这是通过在组成渐变层的生长和弛豫期间引入具有多个穿透位错基本上均匀分布在其表面上的半导体层作为起始层和/或至少一个中间层来实现的。半导体层可以包括接近半导体层的表面并且穿透位错均匀分布在其中的晶种层。

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