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1. 发明申请

US20140210098A1 TECHNIQUES FOR ENHANCING FRACTURE RESISTANCE OF INTERCONNECTS 有权
标题翻译：提高互连电阻的技术
公开(公告)号：US20140210098A1
公开(公告)日：2014-07-31
申请号：US13753245
申请日：2013-01-29
申请人： Christopher J. Jezewski , Mauro J. Kobrinsky , Daniel Pantuso , Siddharth B. Bhingarde , Michael P. O'Day
发明人： Christopher J. Jezewski , Mauro J. Kobrinsky , Daniel Pantuso , Siddharth B. Bhingarde , Michael P. O'Day
IPC分类号： H01L23/00
CPC分类号： H01L23/562 , H01L23/293 , H01L23/481 , H01L23/522 , H01L23/5221 , H01L23/5226 , H01L23/528 , H01L23/5329 , H01L23/535 , H01L23/5381 , H01L23/5386 , H01L2924/0002 , H01L2924/00
摘要： Techniques and structure are disclosed for enhancing fracture resistance of back-end interconnects and other such interconnect structures by increasing via density. Increased via density can be provided, for example, within the filler/dummified portion(s) of adjacent circuit layers within a die. In some cases, an electrically isolated (floating) filler line of an upper circuit layer may include a via which lands on a floating filler line of a lower circuit layer in a region corresponding to where the filler lines cross/intersect. In some such cases, the floating filler line of the upper circuit layer may be formed as a dual-damascene structure including such a via. In some embodiments, a via similarly may be provided between a floating filler line of the upper circuit layer and a sufficiently electrically isolated interconnect line of the lower circuit layer. The techniques/structure can be used to provide mechanical integrity for the die.
摘要翻译：公开了通过增加通孔密度来提高后端互连和其它这种互连结构的抗断裂性的技术和结构。可以例如在模具内的相邻电路层的填充/加工部分内提供通孔密度的增加。在一些情况下，上电路层的电隔离（浮置）填充线可以包括在对应于填充线交叉/相交的区域中的下电路层的浮动填充线上的通孔。在一些这样的情况下，上电路层的浮动填充线可以形成为包括这种通孔的双镶嵌结构。在一些实施例中，可以在上电路层的浮动填充线和下电路层的充分电隔离的互连线之间提供通孔。技术/结构可用于为模具提供机械完整性。

2. 发明授权

US06525419B1 Thermally coupling electrically decoupling cooling device for integrated circuits 失效
公开(公告)号：US06525419B1
公开(公告)日：2003-02-25
申请号：US10076680
申请日：2002-02-14
申请人： Timothy L. Deeter , Thomas Marieb , Daniel Murray , Daniel Pantuso , Sarangapani Sista
发明人： Timothy L. Deeter , Thomas Marieb , Daniel Murray , Daniel Pantuso , Sarangapani Sista
IPC分类号： H01L2334
CPC分类号： H01L23/3735 , H01L23/367 , H01L2924/0002 , H01L2924/00
摘要： A thermally coupling electrically decoupling cooling device is described. The cooling device may be thermally disposed between a self-heating electrically conductive line and a semiconductor substrate to cool the line by transferring heat from the line to the substrate while blocking flow of current from the line to the substrate. The cooling device may contain a thermally conductive structure, such as a stack of vias and lines, to conduct heat away from the electrically conductive line, and a current blocking structure, such as a reverse biased diode or a capacitor, to block current flow into the substrate. Specific current blocking structures include a reverse biased diode containing an n-doped region and a p-doped region disposed between the thermally conductive structure and the substrate, and a capacitor containing a dielectric layer disposed between the thermally conductive structure and the semiconductor substrate.

3. 发明申请

US20160027717A1 INTEGRATED THERMOELECTRIC COOLING 审中-公开
标题翻译：集成式热电冷却
公开(公告)号：US20160027717A1
公开(公告)日：2016-01-28
申请号：US14775487
申请日：2013-06-18
申请人： Lei JIANG , Edwin B. RAMAYYA , Daniel PANTUSO , Rafael RIOS , Kelin J. KUHN , Selyon KIM
发明人： Lei Jang , Edwin B. Ramayya , Daniel Pantuso , Rafael Rios , Kelin J. Kuhn , Seiyon Kim
IPC分类号： H01L23/38 , H01L21/8238 , H05K1/18 , H01L27/092
CPC分类号： H01L23/38 , H01L21/8238 , H01L27/092 , H01L2224/16225 , H01L2924/15311 , H05K1/181 , H05K2201/10166
摘要： Embodiments of the present disclosure describe techniques and configurations for integrated thermoelectric cooling. In one embodiment, a cooling assembly includes a semiconductor substrate, first circuitry disposed on the semiconductor substrate and configured to generate heat when in operation and second circuitry disposed on the semiconductor substrate and configured to remove the heat by thermoelectric cooling. Other embodiments may be described and/or claimed.
摘要翻译：本公开的实施例描述了用于集成热电冷却的技术和配置。在一个实施例中，冷却组件包括半导体衬底，第一电路设置在半导体衬底上并且被配置为在操作时产生热量，第二电路设置在半导体衬底上并且被配置为通过热电冷却去除热量。可以描述和/或要求保护其他实施例。

4. 发明授权

US06646340B2 Thermally coupling electrically decoupling cooling device for integrated circuits 有权
标题翻译：用于集成电路的热耦合电去耦冷却装置
公开(公告)号：US06646340B2
公开(公告)日：2003-11-11
申请号：US10339134
申请日：2003-01-08
申请人： Timothy L. Deeter , Thomas Marieb , Daniel Murray , Daniel Pantuso , Sarangapani Sista
发明人： Timothy L. Deeter , Thomas Marieb , Daniel Murray , Daniel Pantuso , Sarangapani Sista
IPC分类号： H01L2334
CPC分类号： H01L23/3735 , H01L23/367 , H01L2924/0002 , H01L2924/00
摘要： A thermally coupling electrically decoupling cooling device is described. The cooling device may be thermally disposed between a self-heating electrically conductive line and a semiconductor substrate to cool the line by transferring heat from the line to the substrate while blocking flow of current from the line to the substrate. The cooling device may contain a thermally conductive structure, such as a stack of vias and lines, to conduct heat away from the electrically conductive line, and a current blocking structure, such as a reverse biased diode or a capacitor, to block current flow into the substrate. Specific current blocking structures include a reverse biased diode containing an n-doped region and a p-doped region disposed between the thermally conductive structure and the substrate, and a capacitor containing a dielectric layer disposed between the thermally conductive structure and the semiconductor substrate.
摘要翻译：描述了热耦合电去耦冷却装置。冷却装置可以热设置在自加热导电线路和半导体衬底之间，以通过将热量从线路传导到衬底来冷却线路，同时阻挡电流从衬底到衬底的流动。冷却装置可以包含导热结构，例如通孔和管线的堆叠，以将热量从导电线路传导出来，以及电流阻塞结构，例如反向偏置二极管或电容器，以阻止电流流入底物。比电流阻挡结构包括含有n掺杂区域和布置在导热结构和衬底之间的p掺杂区域的反向偏置二极管，以及包含布置在导热结构和半导体衬底之间的电介质层的电容器。

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