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1. 发明授权

US08195919B1 Handling multi-cycle integer operations for a multi-threaded processor 有权
标题翻译：处理多线程处理器的多循环整数运算
公开(公告)号：US08195919B1
公开(公告)日：2012-06-05
申请号：US11927177
申请日：2007-10-29
申请人： Christopher H. Olson , Robert T. Golla , Manish Shah , Jeffrey S. Brooks
发明人： Christopher H. Olson , Robert T. Golla , Manish Shah , Jeffrey S. Brooks
IPC分类号： G06F13/00
CPC分类号： G06F12/0842 , G06F9/3001 , G06F9/30043 , G06F9/3824 , G06F12/0855
摘要： Determining an effective address of a memory with a three-operand add operation in single execution cycle of a multithreaded processor that can access both segmented memory and non-segmented memory. During that cycle, the processor determines whether a memory segment base is zero. If the segment base is zero, the processor can access a memory location at the effective address without adding the segment base. If the segment base is not zero, such as when executing legacy code, the processor consumes another cycle to add the segment base to the effective address. Similarly, the processor consumes another cycle if the effective address or the linear address is misaligned. An integer execution unit that performs the three-operand add using a carry-save adder coupled to a carry look-ahead adder. If the segment base is not zero, the effective address is fed back through the integer execution unit to add the segment base.
摘要翻译：在可以访问分段存储器和非分段存储器的多线程处理器的单个执行周期中确定具有三操作数添加操作的存储器的有效地址。在该周期期间，处理器确定存储器段基数是否为零。如果分段基数为零，则处理器可以在有效地址的情况下访问存储器位置，而不添加分段基。如果段基数不为零，例如执行遗留代码时，处理器消耗另一个周期，将段基数添加到有效地址。类似地，如果有效地址或线性地址不对齐，则处理器消耗另一个周期。整数执行单元，其使用耦合到进位先行加法器的进位保存加法器来执行三运算加法。如果段基数不为零，则通过整数执行单元反馈有效地址以添加段基。

2. 发明授权

US08099586B2 Branch misprediction recovery mechanism for microprocessors 有权
标题翻译：微处理器分支错误预测恢复机制
公开(公告)号：US08099586B2
公开(公告)日：2012-01-17
申请号：US12346349
申请日：2008-12-30
申请人： Yuan C. Chou , Robert T. Golla , Mark A. Luttrell , Paul J. Jordan , Manish Shah
发明人： Yuan C. Chou , Robert T. Golla , Mark A. Luttrell , Paul J. Jordan , Manish Shah
IPC分类号： G06F9/00
CPC分类号： G06F9/3844 , G06F9/3863
摘要： A system and method for reducing branch misprediction penalty. In response to detecting a mispredicted branch instruction, circuitry within a microprocessor identifies a predetermined condition prior to retirement of the branch instruction. Upon identifying this condition, the entire corresponding pipeline is flushed prior to retirement of the branch instruction, and instruction fetch is started at a corresponding address of an oldest instruction in the pipeline immediately prior to the flushing of the pipeline. The correct outcome is stored prior to the pipeline flush. In order to distinguish the mispredicted branch from other instructions, identification information may be stored alongside the correct outcome. One example of the predetermined condition being satisfied is in response to a timer reaching a predetermined threshold value, wherein the timer begins incrementing in response to the mispredicted branch detection and resets at retirement of the mispredicted branch.
摘要翻译：减少分支误判处罚的系统和方法。响应于检测到错误的分支指令，微处理器内的电路在退出分支指令之前识别预定的条件。在识别该条件之后，在分支指令退出之前将整个对应的流水线冲洗，并且在冲洗流水线之前在管道中的最早的指令的对应地址开始指令提取。在管道冲洗之前存储正确的结果。为了将错误预测的分支与其他指令区分开，识别信息可以与正确的结果一起存储。满足预定条件的一个示例是响应于定时器达到预定阈值，其中定时器响应于错误预测的分支检测而开始递增，并且在退出预测分支时重置。

3. 发明申请

US20100169611A1 BRANCH MISPREDICTION RECOVERY MECHANISM FOR MICROPROCESSORS 有权
标题翻译：用于微处理器的分支机构故障恢复机制
公开(公告)号：US20100169611A1
公开(公告)日：2010-07-01
申请号：US12346349
申请日：2008-12-30
申请人： Yuan C. Chou , Robert T. Golla , Mark A. Luttrell , Paul J. Jordan , Manish Shah
发明人： Yuan C. Chou , Robert T. Golla , Mark A. Luttrell , Paul J. Jordan , Manish Shah
IPC分类号： G06F9/312
CPC分类号： G06F9/3844 , G06F9/3863
摘要： A system and method for reducing branch misprediction penalty. In response to detecting a mispredicted branch instruction, circuitry within a microprocessor identifies a predetermined condition prior to retirement of the branch instruction. Upon identifying this condition, the entire corresponding pipeline is flushed prior to retirement of the branch instruction, and instruction fetch is started at a corresponding address of an oldest instruction in the pipeline immediately prior to the flushing of the pipeline. The correct outcome is stored prior to the pipeline flush. In order to distinguish the mispredicted branch from other instructions, identification information may be stored alongside the correct outcome. One example of the predetermined condition being satisfied is in response to a timer reaching a predetermined threshold value, wherein the timer begins incrementing in response to the mispredicted branch detection and resets at retirement of the mispredicted branch.
摘要翻译：减少分支误判处罚的系统和方法。响应于检测到错误的分支指令，微处理器内的电路在退出分支指令之前识别预定的条件。在识别该条件之后，在分支指令退出之前将整个对应的流水线冲洗，并且在冲洗流水线之前在管道中的最早的指令的对应地址开始指令提取。在管道冲洗之前存储正确的结果。为了将错误预测的分支与其他指令区分开，识别信息可以与正确的结果一起存储。满足预定条件的一个示例是响应于定时器达到预定阈值，其中定时器响应于错误预测的分支检测而开始递增，并且在退出预测分支时重置。

4. 发明授权

US07383403B1 Concurrent bypass to instruction buffers in a fine grain multithreaded processor 有权
标题翻译：并发绕过细粒度多线程处理器中的指令缓冲区
公开(公告)号：US07383403B1
公开(公告)日：2008-06-03
申请号：US10881169
申请日：2004-06-30
申请人： Jama I. Barreh , Manish Shah , Robert T. Golla
发明人： Jama I. Barreh , Manish Shah , Robert T. Golla
IPC分类号： G06F12/00
CPC分类号： G06F12/0842 , G06F9/3808 , G06F9/3824 , G06F9/3851 , G06F12/0888 , G06F12/0893
摘要： In one embodiment, a processor comprises a plurality of instruction buffers, an instruction cache coupled to supply instructions to the plurality of instruction buffers, and a cache miss unit coupled to the instruction cache. Each of the plurality of instruction buffers is configured to store instructions fetched from a respective thread of a plurality of threads. The cache miss unit is configured to monitor cache misses in the instruction cache. Particularly, the cache miss unit is configured to detect which of the plurality of threads experience a cache miss to a cache line. Responsive to a return of the cache line for storage in the instruction cache, the cache miss unit is configured to concurrently cause at least one instruction from the cache line to be stored in each of the plurality of instruction buffers that corresponds to one of the plurality of threads which experienced the cache miss to the cache line.
摘要翻译：在一个实施例中，处理器包括多个指令缓冲器，耦合到向多个指令缓冲器提供指令的指令高速缓存器，以及耦合到指令高速缓存器的高速缓存未命中单元。多个指令缓冲器中的每一个被配置为存储从多个线程的相应线程获取的指令。高速缓存未命中单元被配置为监视指令高速缓存中的高速缓存未命中。特别地，高速缓存未命中单元被配置为检测多个线程中的哪个线程经历高速缓存未命中到高速缓存线。响应于高速缓存行的返回以存储在指令高速缓存中，高速缓存未命中单元被配置为同时使得来自高速缓存行的至少一条指令被存储在与多个指令之一相对应的多个指令缓冲器中的每一个中的线程经历高速缓存未命中到高速缓存行。

5. 发明授权

US07747771B1 Register access protocol in a multihreaded multi-core processor 有权
标题翻译：在多线程多核处理器中注册访问协议
公开(公告)号：US07747771B1
公开(公告)日：2010-06-29
申请号：US10881178
申请日：2004-06-30
申请人： Manish Shah , Robert T. Golla , Mark A. Luttrell , Gregory F. Grohoski
发明人： Manish Shah , Robert T. Golla , Mark A. Luttrell , Gregory F. Grohoski
IPC分类号： G06F15/16 , G06F15/76 , G06F13/00
CPC分类号： G06F15/16
摘要： A method and mechanism for managing access to a plurality of registers in a processing device are contemplated. A processing device includes multiple nodes coupled to a ring bus, each of which include one or more registers which may be accessed by processes executing within the device. Also coupled to the ring bus is a ring control unit which is configured to initiate transactions targeted to nodes on the ring bus. Each of the nodes are configured receive and process bus transaction with a fixed latency whether or not the first transaction is targeted to the receiving node. The ring control unit is configured to periodically convey idle transactions on the ring bus in order to allow nodes responding to indeterminate transactions to gain access to the bus.
摘要翻译：考虑了用于管理对处理设备中的多个寄存器的访问的方法和机制。处理设备包括耦合到环形总线的多个节点，每个节点包括一个或多个可由设备内执行的进程访问的寄存器。还耦合到环形总线的环控制单元被配置为发起针对环形总线上的节点的事务。每个节点被配置为具有固定延迟的接收和处理总线事务，无论第一个事务是否针对接收节点。环控制单元被配置为周期性地传送环总线上的空闲事务，以便允许节点响应不确定的事务来访问总线。

6. 发明授权

US07571284B1 Out-of-order memory transactions in a fine-grain multithreaded/multi-core processor 有权
标题翻译：细粒度多线程/多核处理器中的乱序存储器事务
公开(公告)号：US07571284B1
公开(公告)日：2009-08-04
申请号：US10880965
申请日：2004-06-30
申请人： Christopher H. Olson , Manish Shah
发明人： Christopher H. Olson , Manish Shah
IPC分类号： G06F12/00 , G06F13/28 , G06F9/38
CPC分类号： G06F13/1657
摘要： A method and apparatus for implementing out-of-order memory transactions in a multithreaded, multicore processor. In the present invention, circular queue comprising a plurality of queue buffers is used to store load data returned by a memory unit in response to a request issued by a processing module, such as a stream processing unit, in a processing core. As requests are issued, a destination queue buffer ID tag is transmitted as part of the request. When the request is returned, that destination number is reflected back and is used to control which queue within the circular queue will be used to store the retuned load data. Separate pointers are used to indicate the order of the queues to be read and the order of the queues to be written. The method and apparatus implemented by the present invention allows out-of-order data to be processed efficiently, thereby improving the performance of a fine grain multithreaded, multi-core processor.
摘要翻译：一种用于在多线程多核处理器中实现无序存储器事务的方法和装置。在本发明中，包括多个队列缓冲器的循环队列用于存储由处理核心中的诸如流处理单元之类的处理模块发出的请求由存储器单元返回的加载数据。当发出请求时，发送目的地队列缓冲区ID标签作为请求的一部分。当返回请求时，该目的地号码将反映回来，并用于控制循环队列中的哪个队列将用于存储重新调用的加载数据。单独的指针用于指示要读取的队列的顺序和要写入的队列的顺序。通过本发明实现的方法和装置可以有效地处理无序数据，从而提高细粒度多线程多核处理器的性能。

7. 发明申请

US20190216472A1 JIG FOR GUIDING PLACEMENT OF FEMORAL COMPONENT OF THE IMPLANT IN KNEE REPLACEMENT SURGERY 审中-公开
公开(公告)号：US20190216472A1
公开(公告)日：2019-07-18
申请号：US16326347
申请日：2017-07-19
申请人： Manish Shah
发明人： Manish Shah
IPC分类号： A61B17/15 , A61F2/38 , A61F2/46
CPC分类号： A61B17/155 , A61F2/3859 , A61F2/461 , A61F2002/3055
摘要： The present jig for guiding placement of femoral component of the implant in a knee replacement surgery (J) is a pre-assembled Jig (J) that ensures precision fit femoral implant for knee replacement based on difference of cuts in millimeters instead of the usual angle measurement in degrees. It avoids intrusion of the intramedullary canal substantially decreasing the risks of embolism. It enables the surgeon to use precise values of depth of cuts obtained from a system for obtaining optimum fit implant as described in patent application number 3896/MUM2015. This enables the surgeon to control precisely the placement of the implant in terms of flexion or extension, varus or valgus, internal or external rotation. It also enables precise placement of the four-in-one cutting block simultaneously with the distal femur cut; ensuring precise placement of knee femoral component of the knee implant. This reduces efforts and time taken during surgery.

8. 发明授权

US07822850B1 Analyzing log files 有权
标题翻译：分析日志文件
公开(公告)号：US07822850B1
公开(公告)日：2010-10-26
申请号：US12013146
申请日：2008-01-11
申请人： Yevgeniy Brikman , Manish Shah , Paul Antinori , Harun Gadatia , Vipin Palawat
发明人： Yevgeniy Brikman , Manish Shah , Paul Antinori , Harun Gadatia , Vipin Palawat
IPC分类号： G06F15/173
CPC分类号： G06F17/30914 , Y10S707/99943
摘要： Described in an example embodiment herein is a method for extracting values from a plurality of data fields from a log file using a grammar file. The plurality of data fields and a procedure for extracting values from the plurality of data fields are defined in the grammar file. Extracted values are analyzed and graphically represented.
摘要翻译：在这里的示例性实施例中描述的是一种从使用语法文件的日志文件中提取多个数据字段的值的方法。多个数据字段和用于从多个数据字段提取值的过程在语法文件中被定义。提取的值被分析和图形化。

9. 发明申请

US20070072193A1 Ligand arrays having controlled feature size, and methods of making and using the same 审中-公开
标题翻译：具有受控特征尺寸的配体阵列，以及制造和使用它们的方法
公开(公告)号：US20070072193A1
公开(公告)日：2007-03-29
申请号：US11237395
申请日：2005-09-27
申请人： Manish Shah
发明人： Manish Shah
IPC分类号： C12Q1/68 , G01N33/53 , C12M3/00
CPC分类号： B01J19/0046 , B01J2219/00378 , B01J2219/00441 , B01J2219/00527 , B01J2219/00605 , B01J2219/00612 , B01J2219/00626 , B01J2219/00637 , B01J2219/00659 , B01J2219/00722 , B01J2219/00725
摘要： Methods and compositions for producing a solid support having a ligand immobilized on a surface thereof, e.g. a ligand array, are provided. Aspects of the methods include: providing a solid support having a bounded feature location on a surface thereof, where the bounded feature location includes a region of the surface at least partially bounded by an electromagnetic radiation modified boundary; and producing a ligand in the feature location. Also provided are systems for practicing the subject methods, as well as devices produced by the methods and methods of using such devices.
摘要翻译：用于生产具有固定在其表面上的配体的固体支持物的方法和组合物，例如，配体阵列。方法的方面包括：提供具有在其表面上的有界特征位置的固体支撑体，其中有界特征位置包括至少部分地由电磁辐射修饰边界界限的表面区域; 并在特征位置产生配体。还提供了用于实践主题方法的系统，以及通过使用这些装置的方法和方法产生的装置。

10. 发明授权

US11622776B2 Jig for guiding placement of femoral component of the implant in knee replacement surgery 有权
公开(公告)号：US11622776B2
公开(公告)日：2023-04-11
申请号：US17239350
申请日：2021-04-23
申请人： Manish Shah
发明人： Manish Shah
IPC分类号： A61B17/15 , A61F2/38 , A61F2/46 , A61F2/30
摘要： The present jig for guiding placement of femoral component of the implant in a knee replacement surgery (J) is a pre-assembled Jig (J) which ensures precision fit femoral implant for knee replacement based on difference of cuts in millimeters instead of the usual angle measurement in degrees. It avoids intrusion of the intramedullary canal substantially decreasing the risks of embolism. It enables the surgeon to use precise values of depth of cuts obtained from a system for obtaining optimum fit implant as described in patent application number 3896/MUM2015. This enables the surgeon to control precisely the placement of the implant in terms of flexion or extension, varus or valgus, internal or external rotation It also enables precise placement of the fourin-one cutting block simultaneously with the distal femur cut; ensuring precise placement of knee femoral component of the knee implant. This reduces efforts and time taken during the surgery.

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