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1. 发明授权

US06314036B1 Method and apparatus for efficiently testing RAMBUS memory devices 失效
标题翻译：用于有效测试RAMBUS存储器件的方法和装置
公开(公告)号：US06314036B1
公开(公告)日：2001-11-06
申请号：US09708692
申请日：2000-11-07
申请人： Christopher B. Cooper , Brian L. Brown , Thanh K. Mai
发明人： Christopher B. Cooper , Brian L. Brown , Thanh K. Mai
IPC分类号： C13
CPC分类号： G11C7/1072
摘要： A RAMBUS dynamic random access memory includes a test control circuit that selectively couples a row address latch to either a row sense control signal or a CMD control signal. In a normal operating mode, the test control circuit couples the row address latch to the row sense control signal so that the row sense control signal both latches a row address and senses a row of memory cells corresponding to the latched address. Prior to conducting a core noise test, the test control circuit couples the row address latch to the CMD control signal so that the row address is latched by the CMD control signal, and the row sense control signal only functions during the core noise test to sense a row corresponding to the latched row. The memory also includes a multiplexer that receives a time-multiplexed data/address bus and simultaneously couples a first part of the data/address bus to an internal data bus and a second part of the data/address bus to an internal address bus.
摘要翻译： RAMBUS动态随机存取存储器包括选择性地将行地址锁存器耦合到行检测控制信号或CMD控制信号的测试控制电路。在正常操作模式下，测试控制电路将行地址锁存器耦合到行读控制信号，使得行读控制信号都锁存行地址并且感测与锁存地址对应的一行存储单元。在进行核心噪声测试之前，测试控制电路将行地址锁存器耦合到CMD控制信号，使得行地址由CMD控制信号锁存，并且行检测控制信号仅在核心噪声测试期间起作用以感测一行对应于锁存行。存储器还包括多路复用器，其接收时间复用的数据/地址总线，并同时将数据/地址总线的第一部分耦合到内部数据总线以及数据/地址总线的第二部分到内部地址总线。

2. 发明授权

US6144598A Method and apparatus for efficiently testing rambus memory devices 失效
标题翻译：用于有效测试rambus存储器件的方法和装置
公开(公告)号：US6144598A
公开(公告)日：2000-11-07
申请号：US351105
申请日：1999-07-06
申请人： Christopher B. Cooper , Brian L. Brown , Thanh K. Mai
发明人： Christopher B. Cooper , Brian L. Brown , Thanh K. Mai
IPC分类号： G01R31/28 , G11C7/10 , G11C11/401 , G11C11/408 , G11C29/34 , G11C29/50 , G11C13/00 , G11C7/00
CPC分类号： G11C7/1072
摘要： A RAMBUS dynamic random access memory includes a test control circuit that selectively couples a row address latch to either a row sense control signal or a CMD control signal. In a normal operating mode, the test control circuit couples the row address latch to the row sense control signal so that the row sense control signal both latches a row address and senses a row of memory cells corresponding to the latched address. Prior to conducting a core noise test, the test control circuit couples the row address latch to the CMD control signal so that the row address is latched by the CMD control signal, and the row sense control signal only functions during the core noise test to sense a row corresponding to the latched row. The memory also includes a multiplexer that receives a time-multiplexed data/address bus and simultaneously couples a first part of the data/address bus to an internal data bus and a second part of the data/address bus to an internal address bus.
摘要翻译： RAMBUS动态随机存取存储器包括选择性地将行地址锁存器耦合到行检测控制信号或CMD控制信号的测试控制电路。在正常操作模式下，测试控制电路将行地址锁存器耦合到行读控制信号，使得行读控制信号都锁存行地址并且感测与锁存地址对应的一行存储单元。在进行核心噪声测试之前，测试控制电路将行地址锁存器耦合到CMD控制信号，使得行地址由CMD控制信号锁存，并且行检测控制信号仅在核心噪声测试期间起作用以感测一行对应于锁存行。存储器还包括多路复用器，其接收时间复用的数据/地址总线，并同时将数据/地址总线的第一部分耦合到内部数据总线以及数据/地址总线的第二部分到内部地址总线。

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