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1. 发明授权

US06808993B2 Ultra-thin gate dielectrics 有权
标题翻译：超薄栅电介质
公开(公告)号：US06808993B2
公开(公告)日：2004-10-26
申请号：US10339783
申请日：2003-01-08
申请人： Christine M. Finnie , Pauline N. Jacob , Nick Lindert , Keith M. Jackson , Kirk Althoff , Jack Hwang , Jack Kavalieros , James R. Mueller
发明人： Christine M. Finnie , Pauline N. Jacob , Nick Lindert , Keith M. Jackson , Kirk Althoff , Jack Hwang , Jack Kavalieros , James R. Mueller
IPC分类号： H01L21336
CPC分类号： H01L21/28202 , H01L21/28185 , H01L21/3144 , H01L21/3185 , H01L21/823857 , H01L29/513 , H01L29/518
摘要： An in-situ ultra dilute ammonia nitridation process and apparatus of the following ultra-thin chemically tailored gate dielectrics: DCE/O2 (Trans 1,2-Dichloroethylene) based ultra-thin gate dielectric; Nitric Oxide (NO) based ultra-thin gate dielectric that has been re-oxidized via a DCE/O2 (Trans 1,2-Dichloroethylene) process; “dry-wet” DCE (Trans 1,2-Dichloroethylene)/O2-H2O/O2) based ultra-thin gate dielectric; and ultra dilute, less than 1E-7 moles NH3/mm2, nitridation of an ultra-thin gate dielectric. A vertical diffusion furnace (VDF) is provided to process the same. The ultra-thin chemically tailored gate dielectrics generated in a VDF with ultra-dilute NH3, below 1E-7 moles NH3/mm2, in-situ nitridation show a performance comparable or better to traditional ex-situ rapid thermal anneal (RTA) processing techniques for 90 nm CMOS technology. These methods replace and remove at least one process layer in the fabrication of CMOS devices using traditional ex-situ RTA processing, decreasing production costs, and improving fabrication cycle time, with equivalent or improved transistor performance.
摘要翻译：一种原位超稀氨氮工艺及以下超薄化学定制栅极电介质的设备：DCE / O2（Trans 1,2--Dichloroethylene））超薄栅极电介质; 已经通过DCE / O2（反式1,2-二氯乙烯）方法再氧化的一氧化氮（NO）基超薄栅极电介质; “干湿”DCE（反式1,2-二氯乙烯）/ O 2 -H 2 O / O 2）基超薄栅极电介质; 并且超稀释，小于1E-7摩尔NH 3 / mm 2，氮化超薄栅极电介质。提供垂直扩散炉（VDF）来处理它。在具有超稀释NH 3，低于1E-7摩尔NH 3 / mm 2的VDF中产生的超薄化学定制的栅极电介质在现场氮化显示出与传统的非原位快速热退火（RTA）相当或更好的性能）90nm CMOS技术的处理技术。这些方法在使用传统的异地RTA处理，降低生产成本和改进制造周期时间的CMOS器件制造中至少替代和去除至少一个工艺层，具有等效或改进的晶体管性能。

2. 发明申请

US20060046399A1 Forming abrupt source drain metal gate transistors 失效
标题翻译：形成突发源极漏极金属栅极晶体管
公开(公告)号：US20060046399A1
公开(公告)日：2006-03-02
申请号：US10925566
申请日：2004-08-25
申请人： Nick Lindert , Suman Datta , Jack Kavalieros , Mark Doczy , Matthew Metz , Justin Brask , Robert Chau , Mark Bohr , Anand Murthy
发明人： Nick Lindert , Suman Datta , Jack Kavalieros , Mark Doczy , Matthew Metz , Justin Brask , Robert Chau , Mark Bohr , Anand Murthy
IPC分类号： H01L21/336
CPC分类号： H01L29/7833 , H01L29/1054 , H01L29/66545 , H01L29/66553 , H01L29/6656
摘要： A gate structure may be utilized as a mask to form source and drain regions. Then the gate structure may be removed to form a gap and spacers may be formed in the gap to define a trench. In the process of forming a trench into the substrate, a portion of the source drain region is removed. Then the substrate is filled back up with an epitaxial material and a new gate structure is formed thereover. As a result, more abrupt source drain junctions may be achieved.
摘要翻译：栅极结构可以用作掩模以形成源区和漏区。然后可以去除栅极结构以形成间隙，并且可以在间隙中形成间隔物以限定沟槽。在将沟槽形成衬底的过程中，去除源极漏极区的一部分。然后用外延材料填充衬底，并在其上形成新的栅极结构。结果，可以实现更突然的源极漏极结。

3. 发明申请

US20100151669A1 FORMING ABRUPT SOURCE DRAIN METAL GATE TRANSISTORS 有权
标题翻译：形成破裂源排水金属栅极晶体管
公开(公告)号：US20100151669A1
公开(公告)日：2010-06-17
申请号：US12713432
申请日：2010-02-26
申请人： Nick Lindert , Suman Datta , Jack Kavalieros , Mark L. Doczy , Matthew V. Metz , Justin K. Brask , Robert S. Chau , Mark Bohr , Anand S. Murthy
发明人： Nick Lindert , Suman Datta , Jack Kavalieros , Mark L. Doczy , Matthew V. Metz , Justin K. Brask , Robert S. Chau , Mark Bohr , Anand S. Murthy
IPC分类号： H01L21/28
CPC分类号： H01L29/7833 , H01L29/1054 , H01L29/66545 , H01L29/66553 , H01L29/6656
摘要： A gate structure may be utilized as a mask to form source and drain regions. Then the gate structure may be removed to form a gap and spacers may be formed in the gap to define a trench. In the process of forming a trench into the substrate, a portion of the source drain region is removed. Then the substrate is filled back up with an epitaxial material and a new gate structure is formed thereover. As a result, more abrupt source drain junctions may be achieved.
摘要翻译：栅极结构可以用作掩模以形成源区和漏区。然后可以去除栅极结构以形成间隙，并且可以在间隙中形成间隔物以限定沟槽。在将沟槽形成衬底的过程中，去除源极漏极区的一部分。然后用外延材料填充衬底，并在其上形成新的栅极结构。结果，可以实现更突然的源极漏极结。

4. 发明授权

US07704833B2 Method of forming abrupt source drain metal gate transistors 失效
标题翻译：形成突发源极漏极金属栅极晶体管的方法
公开(公告)号：US07704833B2
公开(公告)日：2010-04-27
申请号：US10925566
申请日：2004-08-25
申请人： Nick Lindert , Suman Datta , Jack Kavalieros , Mark L. Doczy , Matthew V. Metz , Justin K. Brask , Robert S. Chau , Mark Bohr , Anand S. Murthy
发明人： Nick Lindert , Suman Datta , Jack Kavalieros , Mark L. Doczy , Matthew V. Metz , Justin K. Brask , Robert S. Chau , Mark Bohr , Anand S. Murthy
IPC分类号： H01L29/76
CPC分类号： H01L29/7833 , H01L29/1054 , H01L29/66545 , H01L29/66553 , H01L29/6656
摘要： A gate structure may be utilized as a mask to form source and drain regions. Then the gate structure may be removed to form a gap and spacers may be formed in the gap to define a trench. In the process of forming a trench into the substrate, a portion of the source drain region is removed. Then the substrate is filled back up with an epitaxial material and a new gate structure is formed thereover. As a result, more abrupt source drain junctions may be achieved.
摘要翻译：栅极结构可以用作掩模以形成源区和漏区。然后可以去除栅极结构以形成间隙，并且可以在间隙中形成间隔物以限定沟槽。在将沟槽形成衬底的过程中，去除源极漏极区的一部分。然后用外延材料填充衬底，并在其上形成新的栅极结构。结果，可以实现更突然的源极漏极结。

5. 发明授权

US07951673B2 Forming abrupt source drain metal gate transistors 有权
标题翻译：形成突发源极漏极金属栅极晶体管
公开(公告)号：US07951673B2
公开(公告)日：2011-05-31
申请号：US12713432
申请日：2010-02-26
申请人： Nick Lindert , Suman Datta , Jack Kavalieros , Mark L. Doczy , Matthew V. Metz , Justin K. Brask , Robert S. Chau , Mark Bohr , Anand S. Murthy
发明人： Nick Lindert , Suman Datta , Jack Kavalieros , Mark L. Doczy , Matthew V. Metz , Justin K. Brask , Robert S. Chau , Mark Bohr , Anand S. Murthy
IPC分类号： H01L29/76
CPC分类号： H01L29/7833 , H01L29/1054 , H01L29/66545 , H01L29/66553 , H01L29/6656
摘要： A gate structure may be utilized as a mask to form source and drain regions. Then the gate structure may be removed to form a gap and spacers may be formed in the gap to define a trench. In the process of forming a trench into the substrate, a portion of the source drain region is removed. Then the substrate is filled back up with an epitaxial material and a new gate structure is formed thereover. As a result, more abrupt source drain junctions may be achieved.
摘要翻译：栅极结构可以用作掩模以形成源区和漏区。然后可以去除栅极结构以形成间隙，并且可以在间隙中形成间隔物以限定沟槽。在将沟槽形成衬底的过程中，去除源极漏极区的一部分。然后用外延材料填充衬底，并在其上形成新的栅极结构。结果，可以实现更突然的源极漏极结。

6. 发明授权

US07439113B2 Forming dual metal complementary metal oxide semiconductor integrated circuits 有权
标题翻译：形成双金属互补金属氧化物半导体集成电路
公开(公告)号：US07439113B2
公开(公告)日：2008-10-21
申请号：US10889535
申请日：2004-07-12
申请人： Mark Doczy , Mitchell Taylor , Justin K. Brask , Jack Kavalieros , Suman Datta , Matthew V. Metz , Robert S. Chau , Jack Hwang
发明人： Mark Doczy , Mitchell Taylor , Justin K. Brask , Jack Kavalieros , Suman Datta , Matthew V. Metz , Robert S. Chau , Jack Hwang
IPC分类号： H01L29/78
CPC分类号： H01L21/823842
摘要： Complementary metal oxide semiconductor metal gate transistors may be formed by depositing a metal layer in trenches formerly inhabited by patterned gate structures. The patterned gate structures may have been formed of polysilicon in one embodiment. The metal layer may have a workfunction most suitable for forming one type of transistor, but is used to form both the n and p-type transistors. The workfunction of the metal layer may be converted, for example, by ion implantation to make it more suitable for use in forming transistors of the opposite type.
摘要翻译：互补金属氧化物半导体金属栅极晶体管可以通过在先前由图案化栅极结构居住的沟槽中沉积金属层来形成。在一个实施例中，图案化栅极结构可以由多晶硅形成。金属层可以具有最适于形成一种类型的晶体管的功函数，但是用于形成n型和p型晶体管。可以例如通过离子注入来转换金属层的功函数，使其更适用于形成相反类型的晶体管。

7. 发明申请

US20090020825A1 Forming dual metal complementary metal oxide semiconductor integrated circuits 审中-公开
标题翻译：形成双金属互补金属氧化物半导体集成电路
公开(公告)号：US20090020825A1
公开(公告)日：2009-01-22
申请号：US12283217
申请日：2008-09-10
申请人： Mark Doczy , Mitchell Taylor , Justin K. Brask , Jack Kavalieros , Suman Datta , Matthew V. Metz , Robert S. Chau , Jack Hwang
发明人： Mark Doczy , Mitchell Taylor , Justin K. Brask , Jack Kavalieros , Suman Datta , Matthew V. Metz , Robert S. Chau , Jack Hwang
IPC分类号： H01L27/092
CPC分类号： H01L21/823842
摘要： Complementary metal oxide semiconductor metal gate transistors may be formed by depositing a metal layer in trenches formerly inhabited by patterned gate structures. The patterned gate structures may have been formed of polysilicon in one embodiment. The metal layer may have a workfunction most suitable for forming one type of transistor, but is used to form both the n and p-type transistors. The workfunction of the metal layer may be converted, for example, by ion implantation to make it more suitable for use in forming transistors of the opposite type.
摘要翻译：互补金属氧化物半导体金属栅极晶体管可以通过在先前由图案化栅极结构居住的沟槽中沉积金属层来形成。在一个实施例中，图案化栅极结构可以由多晶硅形成。金属层可以具有最适于形成一种类型的晶体管的功函数，但是用于形成n型和p型晶体管。可以例如通过离子注入来转换金属层的功函数，使其更适用于形成相反类型的晶体管。

8. 发明申请

US20060006522A1 Forming dual metal complementary metal oxide semiconductor integrated circuits 有权
公开(公告)号：US20060006522A1
公开(公告)日：2006-01-12
申请号：US10889535
申请日：2004-07-12
申请人： Mark Doczy , Mitchell Taylor , Justin Brask , Jack Kavalieros , Suman Datta , Matthew Metz , Robert Chau , Jack Hwang
发明人： Mark Doczy , Mitchell Taylor , Justin Brask , Jack Kavalieros , Suman Datta , Matthew Metz , Robert Chau , Jack Hwang
IPC分类号： H01L23/14
CPC分类号： H01L21/823842
摘要： Complementary metal oxide semiconductor metal gate transistors may be formed by depositing a metal layer in trenches formerly inhabited by patterned gate structures. The patterned gate structures may have been formed of polysilicon in one embodiment. The metal layer may have a workfunction most suitable for forming one type of transistor, but is used to form both the n and p-type transistors. The workfunction of the metal layer may be converted, for example, by ion implantation to make it more suitable for use in forming transistors of the opposite type.

9. 发明授权

US09934976B2 Methods of forming low interface resistance rare earth metal contacts and structures formed thereby 有权
公开(公告)号：US09934976B2
公开(公告)日：2018-04-03
申请号：US12317180
申请日：2008-12-18
申请人： Niloy Mukherjee , Matt Metz , Gilbert Dewey , Jack Kavalieros , Robert S Chau
发明人： Niloy Mukherjee , Matt Metz , Gilbert Dewey , Jack Kavalieros , Robert S Chau
IPC分类号： H01L21/285 , H01L21/768
CPC分类号： H01L21/28518 , H01L21/76814
摘要： Methods and associated structures of forming a microelectronic device are described. Those methods may include forming a contact opening in an inter layer dielectric (ILD) disposed on a substrate, wherein a source/drain contact area is exposed, forming a rare earth metal layer on the source/drain contact area, forming a transition metal layer on the rare earth metal layer; and annealing the rare earth metal layer and the transition metal layer to form a metal silicide stack structure.

10. 发明授权

US08816394B2 Field effect transistor with narrow bandgap source and drain regions and method of fabrication 有权
标题翻译：具有窄带隙源极和漏极区域的场效应晶体管及其制造方法
公开(公告)号：US08816394B2
公开(公告)日：2014-08-26
申请号：US14137804
申请日：2013-12-20
申请人： Robert S. Chau , Suman Datta , Jack Kavalieros , Justin K. Brask , Mark L. Doczy , Matthew Metz
发明人： Robert S. Chau , Suman Datta , Jack Kavalieros , Justin K. Brask , Mark L. Doczy , Matthew Metz
IPC分类号： H01L29/66
CPC分类号： H01L29/7848 , H01L29/0649 , H01L29/0847 , H01L29/1033 , H01L29/16 , H01L29/20 , H01L29/201 , H01L29/207 , H01L29/267 , H01L29/41783 , H01L29/4236 , H01L29/452 , H01L29/517 , H01L29/66522 , H01L29/66628 , H01L29/66636 , H01L29/66795 , H01L29/78 , H01L29/7827 , H01L29/7836 , H01L29/785 , H01L29/78603 , H01L29/78618 , H01L29/78681
摘要： A transistor having a narrow bandgap semiconductor source/drain region is described. The transistor includes a gate electrode formed on a gate dielectric layer formed on a silicon layer. A pair of source/drain regions are formed on opposite sides of the gate electrode wherein said pair of source/drain regions comprise a narrow bandgap semiconductor film formed in the silicon layer on opposite sides of the gate electrode.
摘要翻译：描述具有窄带隙半导体源极/漏极区域的晶体管。晶体管包括形成在形成于硅层上的栅介质层上的栅电极。一对源极/漏极区域形成在栅电极的相对侧上，其中所述一对源极/漏极区域包括形成在栅电极的相对侧上的硅层中的窄带隙半导体膜。

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