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1. 发明授权

US06762627B1 Switched capacitor peak detector with variable time constant asymmetrical filtering 有权
标题翻译：具有可变时间常数不对称滤波的开关电容峰值检测器
公开(公告)号：US06762627B1
公开(公告)日：2004-07-13
申请号：US10404936
申请日：2003-03-31
申请人： Christian Gater
发明人： Christian Gater
IPC分类号： G01R1900
CPC分类号： G01R19/04
摘要： A peak detector employs switched capacitor filtering to implement long time constant and variable attack and decay characteristics. In one embodiment, the peak detector includes a first switch, a rectifier, a first capacitor and a second switch in the attack path, and a third switch, a second capacitor and a fourth switch in the decay path. The peak detector further includes a third capacitor coupled to the attack and decay paths and having a capacitance greater than the capacitance of the first and second capacitors. In operation, the attack path is activated by alternately closing the first and second switches to sample the input signal and generate an output voltage at the third capacitor indicative of the peak voltage value of the input signal. The second circuit path is activated by alternately closing the third and fourth switches to decrease the output voltage at the third capacitor.
摘要翻译：峰值检测器采用开关电容滤波来实现长时间常数和可变的攻击和衰减特性。在一个实施例中，峰值检测器包括攻击路径中的第一开关，整流器，第一电容器和第二开关，以及衰减路径中的第三开关，第二电容器和第四开关。峰值检测器还包括耦合到攻击和衰减路径并且具有大于第一和第二电容器的电容的电容的第三电容器。在操作中，通过交替关闭第一和第二开关来对输入信号进行采样来激活攻击路径，并且在第三电容器处产生指示输入信号的峰值电压值的输出电压。通过交替关闭第三和第四开关来激活第二电路路径，以减小第三电容器的输出电压。

2. 发明授权

US07315585B2 Clock-less serial data interface using a single pin 有权
标题翻译：使用单个引脚的无时钟串行数据接口
公开(公告)号：US07315585B2
公开(公告)日：2008-01-01
申请号：US10776154
申请日：2004-02-11
申请人： Christian Gater
发明人： Christian Gater
IPC分类号： H04L27/00
CPC分类号： H04L25/4902
摘要： A data communication method for receiving digital data on a data terminal includes receiving data pulses having a first pulse separation to represent a first logical data value and a second pulse separation to represent a second logical data value, generating a voltage ramp signal, resetting the voltage ramp signal at a first delay after the leading edge of each data pulse, regenerating the voltage ramp signal at a first time period after the resetting of the voltage ramp signal, detecting the voltage value of the voltage ramp signal at the leading edge of each data pulse, and generating a data output signal associated with each data pulse. The data output signal has a first logical state when the voltage value of the voltage ramp signal is less than a threshold value and a second logical state when the voltage value of the voltage ramp signal is greater than the threshold value.
摘要翻译：一种用于在数据终端上接收数字数据的数据通信方法包括接收具有第一脉冲间隔的数据脉冲，以表示第一逻辑数据值和第二脉冲间隔以表示第二逻辑数据值，产生电压斜坡信号，复位电压在每个数据脉冲的前沿之后的第一延迟处的斜坡信号，在电压斜坡信号复位之后的第一时间段再生电压斜坡信号，检测每个数据的前沿处的电压斜坡信号的电压值并且产生与每个数据脉冲相关联的数据输出信号。当电压斜坡信号的电压值小于阈值时，数据输出信号具有第一逻辑状态，当电压斜坡信号的电压值大于阈值时，数据输出信号具有第二逻辑状态。

3. 发明授权

US07843148B2 Driving multiple parallel LEDs with reduced power supply ripple 有权
标题翻译：驱动多个并联LED，降低电源纹波
公开(公告)号：US07843148B2
公开(公告)日：2010-11-30
申请号：US12099729
申请日：2008-04-08
申请人： Christian Gater , Roel Van Ettinger
发明人： Christian Gater , Roel Van Ettinger
IPC分类号： H05B37/02
CPC分类号： H05B33/0815 , G09G3/342 , G09G2320/064 , H05B33/0827
摘要： An LED driver is disclosed that drives LEDs connected in parallel. Instead of applying current to all the parallel-connected LEDs at the same time, under control of a common PWM brightness control signal, the application of current to each parallel path is staggered by using staggered brightness control signals. The turning on of the LEDs in the different parallel paths will have the same duty cycle but will be out of phase. This reduces ripple in the power supply by reducing the magnitude of the instantaneous current sink. In one embodiment, a shift register contains a binary representation of the PWM duty cycle, and a clock shifts the bits along the shift register. The PWM brightness control signals for each parallel path of LEDs are tapped from different positions along the shift register so that the PWM brightness control signals are identical but staggered.
摘要翻译：公开了驱动并联连接的LED的LED驱动器。在普通的PWM亮度控制信号的控制下，不是同时对所有并联连接的LED施加电流，而是通过使用交错的亮度控制信号将每个并行路径的电流施加交错。不同并行路径中的LED的导通将具有相同的占空比，但是将不同步。这通过减小瞬时电流吸收器的幅度来减少电源中的纹波。在一个实施例中，移位寄存器包含PWM占空比的二进制表示，并且时钟沿着移位寄存器移位位。 LED的每个并行路径的PWM亮度控制信号从沿着移位寄存器的不同位置被抽头，使得PWM亮度控制信号相同而交错。

4. 发明申请

US20090033243A1 LED Controller IC Using Only One Pin to Dim and Set a Maximum LED Current 有权
标题翻译： LED控制器IC只使用一个引脚来调光并设置最大LED电流
公开(公告)号：US20090033243A1
公开(公告)日：2009-02-05
申请号：US11832321
申请日：2007-08-01
申请人： Christian Gater
发明人： Christian Gater
IPC分类号： H05B41/36
CPC分类号： H05B33/0848 , H05B33/0827
摘要： An LED driver IC is described that uses a single pin to both set the maximum current through one or more driven LEDs and variably control the brightness of the LEDs. A single resistor is connected to the control pin of the IC, where the value of the resistor sets the maximum current through the LEDs. A PWM source, outputting a pulse train at a particular duty cycle, is connected to the other end of the resistor, where the duty cycle controls the LED brightness level. When the PWM signal is low (e.g. ground), a sample and hold circuit connects the output of a feedback control voltage to an Imax current source to set a maximum current based on the external resistor value. An inverse of the duty cycle of the PWM controller controls a current Idim that is subtracted from the maximum current Imax set by the resistor. This difference current is used to control drivers for the LEDs.
摘要翻译：描述了一种LED驱动器IC，其使用单个引脚来设置通过一个或多个驱动LED的最大电流并且可变地控制LED的亮度。单个电阻连接到IC的控制引脚，其中电阻值通过LED设置最大电流。以特定占空比输出脉冲序列的PWM源连接到电阻器的另一端，其中占空比控制LED亮度级别。当PWM信号为低电平（例如接地）时，采样和保持电路将反馈控制电压的输出连接到Imax电流源，以根据外部电阻值设置最大电流。 PWM控制器的占空比的倒数控制从电阻器设置的最大电流Imax中减去的电流Idim。该差分电流用于控制LED的驱动器。

5. 发明授权

US06411130B1 Method and system for reliably providing a lock indication 有权
标题翻译：可靠地提供锁指示的方法和系统
公开(公告)号：US06411130B1
公开(公告)日：2002-06-25
申请号：US09769059
申请日：2001-01-23
申请人： Christian Gater
发明人： Christian Gater
IPC分类号： H03D1300
CPC分类号： H03D13/003
摘要： In a first aspect, a lock indicator circuit is disclosed. The lock indicator comprises a first circuit for providing a first beat signal; and a second circuit for providing a second beat signal. A reference clock signal and a recovered clock signal are provided in a reversed manner to the first and second circuits. In a second aspect, a method for providing a lock indication of a circuit is disclosed. The method comprises the steps of providing a first and second beat signals; and utilizing the first and second beat signals to determine if a lock condition has occurred. A system and method in accordance with the present invention indicates a lock to the desired reference clock and provides an error or out of lock condition if the recovered frequency is at a harmonic or subharmonic of the reference frequency. This ability to avoid a false lock indication requires very little additional circuitry. A further improvement is that the circuit correctly indicates out of lock condition even in the absence of a reference frequency, caused for instance by a broken signal connection.
摘要翻译：在第一方面，公开了一种锁定指示器电路。锁定指示器包括用于提供第一拍子信号的第一电路; 以及用于提供第二拍频信号的第二电路。参考时钟信号和恢复的时钟信号以与第一和第二电路相反的方式提供。在第二方面，公开了一种用于提供电路的锁定指示的方法。该方法包括提供第一和第二拍频信号的步骤; 以及利用第一和第二拍频信号来确定是否发生了锁定状态。如果恢复的频率处于参考频率的谐波或次谐波，则根据本发明的系统和方法指示锁定到期望的参考时钟并且提供错误或失锁状态。这种避免假锁指示的能力需要很少的附加电路。进一步的改进是即使在没有参考频率的情况下，电路也正确地指示出锁定状态，例如由于信号断开而导致的。

6. 发明申请

US20090251071A1 Driving Multiple Parallel LEDs with Reduced Power Supply Ripple 有权
标题翻译：驱动具有降低电源纹波的多个并联LED
公开(公告)号：US20090251071A1
公开(公告)日：2009-10-08
申请号：US12099729
申请日：2008-04-08
申请人： Christian Gater , Roel Van Ettinger
发明人： Christian Gater , Roel Van Ettinger
IPC分类号： H05B37/02
CPC分类号： H05B33/0815 , G09G3/342 , G09G2320/064 , H05B33/0827
摘要： An LED driver is disclosed that drives LEDs connected in parallel. Instead of applying current to all the parallel-connected LEDs at the same time, under control of a common PWM brightness control signal, the application of current to each parallel path is staggered by using staggered brightness control signals. The turning on of the LEDs in the different parallel paths will have the same duty cycle but will be out of phase. This reduces ripple in the power supply by reducing the magnitude of the instantaneous current sink. In one embodiment, a shift register contains a binary representation of the PWM duty cycle, and a clock shifts the bits along the shift register. The PWM brightness control signals for each parallel path of LEDs are tapped from different positions along the shift register so that the PWM brightness control signals are identical but staggered.
摘要翻译：公开了驱动并联连接的LED的LED驱动器。在普通的PWM亮度控制信号的控制下，不是同时对所有并联连接的LED施加电流，而是通过使用交错的亮度控制信号将每个并行路径的电流施加交错。不同并行路径中的LED的导通将具有相同的占空比，但是将不同步。这通过减小瞬时电流吸收器的幅度来减少电源中的纹波。在一个实施例中，移位寄存器包含PWM占空比的二进制表示，并且时钟沿移位寄存器移位位。 LED的每个并行路径的PWM亮度控制信号从沿着移位寄存器的不同位置被抽头，使得PWM亮度控制信号相同而交错。

7. 发明授权

US07528555B2 LED controller IC using only one pin to dim and set a maximum LED current 有权
标题翻译： LED控制器IC仅使用一个引脚来调光并设置最大LED电流
公开(公告)号：US07528555B2
公开(公告)日：2009-05-05
申请号：US11832321
申请日：2007-08-01
申请人： Christian Gater
发明人： Christian Gater
IPC分类号： G05F1/00
CPC分类号： H05B33/0848 , H05B33/0827
摘要： An LED driver IC is described that uses a single pin to both set the maximum current through one or more driven LEDs and variably control the brightness of the LEDs. A single resistor is connected to the control pin of the IC, where the value of the resistor sets the maximum current through the LEDs. A PWM source, outputting a pulse train at a particular duty cycle, is connected to the other end of the resistor, where the duty cycle controls the LED brightness level. When the PWM signal is low (e.g. ground), a sample and hold circuit connects the output of a feedback control voltage to an Imax current source to set a maximum current based on the external resistor value. An inverse of the duty cycle of the PWM controller controls a current Idim that is subtracted from the maximum current Imax set by the resistor. This difference current is used to control drivers for the LEDs.
摘要翻译：描述了一种LED驱动器IC，其使用单个引脚来设置通过一个或多个驱动LED的最大电流并且可变地控制LED的亮度。单个电阻连接到IC的控制引脚，其中电阻值通过LED设置最大电流。以特定占空比输出脉冲序列的PWM源连接到电阻器的另一端，其中占空比控制LED亮度级别。当PWM信号为低电平（例如接地）时，采样和保持电路将反馈控制电压的输出连接到Imax电流源，以根据外部电阻值设置最大电流。 PWM控制器的占空比的倒数控制从电阻器设置的最大电流Imax中减去的电流Idim。该差分电流用于控制LED的驱动器。

8. 发明申请

US20080248765A1 Superheterodyne Receiver with Switchable Local Oscillator Frequency and Reconfigurable IF Filter Characteristics 审中-公开
标题翻译：具有可切换本地振荡器频率和可重构IF滤波器特性的超外差接收器
公开(公告)号：US20080248765A1
公开(公告)日：2008-10-09
申请号：US11696706
申请日：2007-04-04
申请人： Christian Gater
发明人： Christian Gater
IPC分类号： H04B1/02
CPC分类号： H04B1/28 , H04B1/1027
摘要： An integrated circuit RF receiver processes multiple RF frequencies without internally changing the local oscillator to receive the multiple signals. No front-end tuner is used. In one embodiment, multiple crystals are connected to pins of the IC. A switch within the IC, controlled by a switch signal, selects one of the crystals as a reference frequency, depending on the frequency of the RF signal desired to be received. The selected reference frequency is applied to an RF synthesizer (a local oscillator) to set the output frequency of the RF synthesizer. The local oscillator signal is then mixed with the incoming RF signal to generate sum and difference signals that need to be filtered by an IF filter. The switch signal also reconfigures the IF filter to change its center frequency and filter bandwidth, based on the requirements of the RF signal data format.
摘要翻译：集成电路RF接收器处理多个RF频率而无需内部改变本地振荡器以接收多个信号。没有使用前端调谐器。在一个实施例中，多个晶体连接到IC的引脚。由开关信号控制的IC内的开关根据期望接收的RF信号的频率，选择晶体之一作为参考频率。所选择的参考频率被施加到RF合成器（本地振荡器）以设置RF合成器的输出频率。然后将本地振荡器信号与输入的RF信号混合以产生需要由IF滤波器滤波的和和差信号。根据RF信号数据格式的要求，开关信号还重新配置IF滤波器以改变其中心频率和滤波器带宽。

9. 发明申请

US20050175120A1 Clock-less serial data interface using a single pin 有权
标题翻译：使用单个引脚的无时钟串行数据接口
公开(公告)号：US20050175120A1
公开(公告)日：2005-08-11
申请号：US10776154
申请日：2004-02-11
申请人： Christian Gater
发明人： Christian Gater
IPC分类号： H04L25/49 , H04L27/06
CPC分类号： H04L25/4902
摘要： A data communication method for receiving digital data on a data terminal includes receiving data pulses having a first pulse separation to represent a first logical data value and a second pulse separation to represent a second logical data value, generating a voltage ramp signal, resetting the voltage ramp signal a first delay after the leading edge of each data pulse, regenerating the voltage ramp signal a first time period after the resetting of the voltage ramp signal, detecting the voltage value of the voltage ramp signal at the leading edge of each data pulse, and generating a data output signal associated with each data pulse. The data output signal has a first logical state when the voltage value of the voltage ramp signal is less than a threshold value and a second logical state when the voltage value of the voltage ramp signal is greater than the threshold value.
摘要翻译：一种用于在数据终端上接收数字数据的数据通信方法包括接收具有第一脉冲间隔的数据脉冲，以表示第一逻辑数据值和第二脉冲间隔以表示第二逻辑数据值，产生电压斜坡信号，复位电压斜坡信号在每个数据脉冲的前沿之后的第一延迟信号，在电压斜坡信号复位之后的第一时间段再生电压斜坡信号，检测每个数据脉冲的前沿处的电压斜坡信号的电压值，并产生与每个数据脉冲相关联的数据输出信号。当电压斜坡信号的电压值小于阈值时，数据输出信号具有第一逻辑状态，当电压斜坡信号的电压值大于阈值时，数据输出信号具有第二逻辑状态。

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