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1. 发明授权

US08211801B2 Method of fabricating complementary metal-oxide-semiconductor (CMOS) device 有权
标题翻译：互补金属氧化物半导体（CMOS）器件的制造方法
公开(公告)号：US08211801B2
公开(公告)日：2012-07-03
申请号：US12874332
申请日：2010-09-02
申请人： Chiu-Hsien Yeh , Chan-Lon Yang , Chin-Cheng Chien , Lien-Fa Hung , Yun-Cheng Kao
发明人： Chiu-Hsien Yeh , Chan-Lon Yang , Chin-Cheng Chien , Lien-Fa Hung , Yun-Cheng Kao
IPC分类号： H01L21/461 , H01L21/302
CPC分类号： H01L29/517 , H01L21/31111 , H01L21/823842 , H01L21/823857 , H01L21/823878 , H01L29/4966 , H01L29/513
摘要： A method of fabricating a CMOS device having high-k dielectric layer and metal gate electrode is provided. First, an isolation structure is formed in a substrate to define a first-type and a second-type MOS regions; an interfacial layer and a high-k dielectric layer are sequentially formed over the substrate; a first and a second cover layers are respectively formed over a portion of the high-k dielectric layer at the first-type MOS region and another portion of the high-k dielectric layer at the second-type MOS region; afterwards, an in-situ etching step is performed to sequentially etch the first and second cover layers using a first etching solution and to etch both the high-k dielectric layer and the interfacial layer using a second etching solution until the substrate is exposed. Wherein, the second etching solution is a mixed etching solution containing the first etching solution.
摘要翻译：提供一种制造具有高k电介质层和金属栅电极的CMOS器件的方法。首先，在衬底中形成隔离结构以限定第一类型和第二类型的MOS区; 在衬底上顺序地形成界面层和高k电介质层; 第一和第二覆盖层分别形成在第一型MOS区的高k电介质层的一部分和第二类型MOS区的高k电介质层的另一部分上; 之后，执行原位蚀刻步骤以使用第一蚀刻溶液顺次蚀刻第一和第二覆盖层，并且使用第二蚀刻溶液蚀刻高k电介质层和界面层，直到基板被暴露。其中，第二蚀刻溶液是含有第一蚀刻溶液的混合蚀刻溶液。

2. 发明授权

US08404591B2 Method of fabricating complementary metal-oxide-semiconductor (CMOS) device 有权
标题翻译：互补金属氧化物半导体（CMOS）器件的制造方法
公开(公告)号：US08404591B2
公开(公告)日：2013-03-26
申请号：US13482044
申请日：2012-05-29
申请人： Chiu-Hsien Yeh , Chan-Lon Yang , Chin-Cheng Chien , Lien-Fa Hung , Yun-Cheng Kao
发明人： Chiu-Hsien Yeh , Chan-Lon Yang , Chin-Cheng Chien , Lien-Fa Hung , Yun-Cheng Kao
IPC分类号： H01L21/461 , H01L21/302
CPC分类号： H01L29/517 , H01L21/31111 , H01L21/823842 , H01L21/823857 , H01L21/823878 , H01L29/4966 , H01L29/513
摘要： A method of fabricating a MOS device comprises steps as follows: An interfacial layer, a high-k dielectric layer and a cover layer on a substrate are sequentially formed. Then an in-situ wet etching step is performed by sequentially using a first etching solution to etch the cover layer and using a second etching solution to etch the high-k dielectric layer and the interfacial layer until the substrate is exposed, wherein the second etching solution is a mixed etching solution containing the first etching solution.
摘要翻译：制造MOS器件的方法包括以下步骤：依次形成界面层，高k电介质层和衬底上的覆盖层。然后，通过依次使用第一蚀刻溶液蚀刻覆盖层并使用第二蚀刻溶液来蚀刻高k电介质层和界面层直到基板被暴露来进行原位湿蚀刻步骤，其中第二蚀刻溶液是含有第一蚀刻溶液的混合蚀刻溶液。

3. 发明授权

US08252515B2 Method for removing photoresist 有权
标题翻译：去除光刻胶的方法
公开(公告)号：US08252515B2
公开(公告)日：2012-08-28
申请号：US12577729
申请日：2009-10-13
申请人： Chin-Cheng Chien , Chan-Lon Yang , Chiu-Hsien Yeh , Che-Hua Hsu , Zhi-Cheng Lee , Shao-Hua Hsu , Cheng-Guo Chen , Shin-Chi Chen , Zhi-Jian Wang
发明人： Chin-Cheng Chien , Chan-Lon Yang , Chiu-Hsien Yeh , Che-Hua Hsu , Zhi-Cheng Lee , Shao-Hua Hsu , Cheng-Guo Chen , Shin-Chi Chen , Zhi-Jian Wang
IPC分类号： G03F7/00 , G03F7/004 , G03F7/40
CPC分类号： H01L21/31133 , G03F7/423 , H01L21/266
摘要： A method for removing a photoresist is disclosed. First, a substrate including a patterned photoresist is provided. Second, an ion implantation is carried out on the substrate. Then, a non-oxidative pre-treatment is carried out on the substrate. The non-oxidative pre-treatment provides hydrogen, a carrier gas and plasma. Later, a photoresist-stripping step is carried out so that the photoresist can be completely removed.
摘要翻译：公开了一种去除光刻胶的方法。首先，提供包括图案化光致抗蚀剂的基板。其次，在基板上进行离子注入。然后，在基板上进行非氧化性预处理。非氧化预处理提供氢气，载气和等离子体。之后，进行光致抗蚀剂剥离工序，使光致抗蚀剂能够被完全除去。

4. 发明授权

US08980753B2 Metal gate transistor and method for fabricating the same 有权
标题翻译：金属栅极晶体管及其制造方法
公开(公告)号：US08980753B2
公开(公告)日：2015-03-17
申请号：US12886580
申请日：2010-09-21
申请人： Yeng-Peng Wang , Chun-Hsien Lin , Chiu-Hsien Yeh , Chin-Cheng Chien , Chan-Lon Yang
发明人： Yeng-Peng Wang , Chun-Hsien Lin , Chiu-Hsien Yeh , Chin-Cheng Chien , Chan-Lon Yang
IPC分类号： H01L21/311 , H01L21/302 , H01L21/461 , C03C15/00 , C03C25/68 , C23F1/00 , B44C1/22 , H01L21/8238
CPC分类号： H01L21/823842 , H01L21/823807 , H01L21/823814
摘要： A method for fabricating a metal gate transistor is disclosed. The method includes the steps of: providing a substrate having a first transistor region and a second transistor region; forming a first metal-oxide semiconductor (MOS) transistor on the first transistor region and a second MOS transistor on the second transistor region, in which the first MOS transistor includes a first dummy gate and the second MOS transistor comprises a second dummy gate; forming a patterned hard mask on the second MOS transistor, in which the hard mask includes at least one metal atom; and using the patterned hard mask to remove the first dummy gate of the first MOS transistor.
摘要翻译：公开了一种用于制造金属栅极晶体管的方法。该方法包括以下步骤：提供具有第一晶体管区域和第二晶体管区域的衬底; 在第一晶体管区域上形成第一金属氧化物半导体（MOS）晶体管，在第二晶体管区域形成第二MOS晶体管，其中第一MOS晶体管包括第一虚拟栅极，第二MOS晶体管包括第二虚拟栅极; 在所述第二MOS晶体管上形成图案化的硬掩模，其中所述硬掩模包括至少一个金属原子; 以及使用图案化的硬掩模去除第一MOS晶体管的第一伪栅极。

5. 发明申请

US20120070995A1 METAL GATE TRANSISTOR AND METHOD FOR FABRICATING THE SAME 有权
标题翻译：金属栅极晶体管及其制造方法
公开(公告)号：US20120070995A1
公开(公告)日：2012-03-22
申请号：US12886580
申请日：2010-09-21
申请人： Yeng-Peng Wang , Chun-Hsien Lin , Chiu-Hsien Yeh , Chin-Cheng Chien , Chan-Lon Yang
发明人： Yeng-Peng Wang , Chun-Hsien Lin , Chiu-Hsien Yeh , Chin-Cheng Chien , Chan-Lon Yang
IPC分类号： H01L21/302
CPC分类号： H01L21/823842 , H01L21/823807 , H01L21/823814
摘要： A method for fabricating a metal gate transistor is disclosed. The method includes the steps of: providing a substrate having a first transistor region and a second transistor region; forming a first metal-oxide semiconductor (MOS) transistor on the first transistor region and a second MOS transistor on the second transistor region, in which the first MOS transistor includes a first dummy gate and the second MOS transistor comprises a second dummy gate; forming a patterned hard mask on the second MOS transistor, in which the hard mask includes at least one metal atom; and using the patterned hard mask to remove the first dummy gate of the first MOS transistor.
摘要翻译：公开了一种用于制造金属栅极晶体管的方法。该方法包括以下步骤：提供具有第一晶体管区域和第二晶体管区域的衬底; 在第一晶体管区域上形成第一金属氧化物半导体（MOS）晶体管，在第二晶体管区域形成第二MOS晶体管，其中第一MOS晶体管包括第一虚拟栅极，第二MOS晶体管包括第二虚拟栅极; 在所述第二MOS晶体管上形成图案化的硬掩模，其中所述硬掩模包括至少一个金属原子; 以及使用图案化的硬掩模去除第一MOS晶体管的第一伪栅极。

6. 发明申请

US20110086499A1 METHOD FOR REMOVING PHOTORESIST 有权
标题翻译：去除光电子的方法
公开(公告)号：US20110086499A1
公开(公告)日：2011-04-14
申请号：US12577729
申请日：2009-10-13
申请人： Chin-Cheng Chien , Chan-Lon Yang , Chiu-Hsien Yeh
发明人： Chin-Cheng Chien , Chan-Lon Yang , Chiu-Hsien Yeh
IPC分类号： H01L21/265 , H01L21/306
CPC分类号： H01L21/31133 , G03F7/423 , H01L21/266
摘要： A method for removing a photoresist is disclosed. First, a substrate including a patterned photoresist is provided. Second, an ion implantation is carried out on the substrate. Then, a non-oxidative pre-treatment is carried out on the substrate. The non-oxidative pre-treatment provides hydrogen, a carrier gas and plasma. Later, a photoresist-stripping step is carried out so that the photoresist can be completely removed.
摘要翻译：公开了一种去除光致抗蚀剂的方法。首先，提供包括图案化光致抗蚀剂的基板。其次，在基板上进行离子注入。然后，在基板上进行非氧化性预处理。非氧化预处理提供氢气，载气和等离子体。之后，进行光致抗蚀剂剥离工序，使光致抗蚀剂能够被完全除去。

7. 发明授权

US08298950B2 Method of etching sacrificial layer 有权
标题翻译：蚀刻牺牲层的方法
公开(公告)号：US08298950B2
公开(公告)日：2012-10-30
申请号：US12830370
申请日：2010-07-05
申请人： Chan-Lon Yang , Yeng-Peng Wang , Chiu-Hsien Yeh
发明人： Chan-Lon Yang , Yeng-Peng Wang , Chiu-Hsien Yeh
IPC分类号： H01L21/311
CPC分类号： H01L21/823842 , H01L21/32134 , H01L21/32135 , H01L27/11 , H01L27/1104
摘要： An exemplary method of etching sacrificial layer includes steps of: providing a substrate formed with a sacrificial layer and defined with a first region and a second region, the sacrificial layer disposed in both the first and second regions; forming a hard mask covering the first region while exposing the second region; performing a first etching process on the sacrificial layer to thin the sacrificial layer while forming a byproduct film overlying the thinned sacrificial layer; performing a second etching process on the byproduct film to remove a portion of the byproduct layer for exposing a portion of the thinned sacrificial layer, while another portion of the byproduct film disposed on sidewalls of the thinned sacrificial layer being remained; and performing a third etching process on the thinned sacrificial layer, to remove the portion of the thinned sacrificial layer exposed in the second etching process.
摘要翻译：蚀刻牺牲层的示例性方法包括以下步骤：提供形成有牺牲层并且由第一区域和第二区域限定的衬底，所述牺牲层设置在第一和第二区域中; 在暴露所述第二区域的同时形成覆盖所述第一区域的硬掩模; 在所述牺牲层上执行第一蚀刻工艺以使所述牺牲层变薄，同时形成覆盖所述薄化的牺牲层的副产物膜; 在副产品膜上执行第二蚀刻工艺以去除副产物层的一部分，用于暴露部分减薄的牺牲层，同时保留设置在减薄的牺牲层的侧壁上的副产物膜的另一部分; 以及对所述减薄的牺牲层执行第三蚀刻工艺，以去除在所述第二蚀刻工艺中暴露的所述薄化牺牲层的所述部分。

8. 发明授权

US08476169B2 Method of making strained silicon channel semiconductor structure 有权
标题翻译：制造应变硅沟道半导体结构的方法
公开(公告)号：US08476169B2
公开(公告)日：2013-07-02
申请号：US13274357
申请日：2011-10-17
申请人： Chan-Lon Yang , Ted Ming-Lang Guo , Chin-I Liao , Chin-Cheng Chien , Shu-Yen Chan , Chun-Yuan Wu
发明人： Chan-Lon Yang , Ted Ming-Lang Guo , Chin-I Liao , Chin-Cheng Chien , Shu-Yen Chan , Chun-Yuan Wu
IPC分类号： H01L21/311
CPC分类号： H01L29/7848 , H01L21/30608 , H01L21/3247 , H01L21/823425 , H01L29/6656 , H01L29/66636
摘要： A method for fabricating a strained channel semiconductor structure includes providing a substrate, forming at least one gate structure on said substrate, performing an etching process to form two recesses in said substrate at opposites sides of said gate structure, the sidewall of said recess being concaved in the direction to said gate structure and forming an included angle with respect to horizontal plane, and performing a pre-bake process to modify the recess such that said included angle between the sidewall of said recess and the horizontal plane is increased.
摘要翻译：一种制造应变通道半导体结构的方法包括提供衬底，在所述衬底上形成至少一个栅极结构，执行蚀刻工艺以在所述衬底的所述栅极结构的相对侧形成两个凹槽，所述凹槽的侧壁为凹面在所述栅极结构的方向上并相对于水平面形成夹角，并且执行预烘烤处理以改变凹部，使得所述凹部的侧壁和水平面之间的所述夹角增加。

9. 发明申请

US20130137243A1 SEMICONDUCTOR PROCESS 有权
标题翻译：半导体工艺
公开(公告)号：US20130137243A1
公开(公告)日：2013-05-30
申请号：US13308513
申请日：2011-11-30
申请人： Chan-Lon Yang , Ching-I Li , Ger-Pin Lin , I-Ming Lai , Yun-San Huang , Chin-I Liao , Chin-Cheng Chien
发明人： Chan-Lon Yang , Ching-I Li , Ger-Pin Lin , I-Ming Lai , Yun-San Huang , Chin-I Liao , Chin-Cheng Chien
IPC分类号： H01L21/20
CPC分类号： H01L29/6656 , H01L29/517 , H01L29/6659 , H01L29/66636 , H01L29/7834 , H01L29/7847 , H01L29/7848
摘要： First, a substrate with a recess is provided in a semiconductor process. Second, an embedded SiGe layer is formed in the substrate. The embedded SiGe layer includes an epitaxial SiGe material which fills up the recess. Then, a pre-amorphization implant (PAI) procedure is carried out on the embedded SiGe layer to form an amorphous region. Next, a source/drain implanting procedure is carried out on the embedded SiGe layer to form a source doping region and a drain doping region. Later, a source/drain annealing procedure is carried out to form a source and a drain in the substrate. At least one of the pre-amorphization implant procedure and the source/drain implanting procedure is carried out in a cryogenic procedure below −30° C.
摘要翻译：首先，在半导体工艺中设置具有凹部的基板。第二，在衬底中形成嵌入的SiGe层。嵌入的SiGe层包括填充凹槽的外延SiGe材料。然后，在嵌入的SiGe层上进行预非晶化植入（PAI）工艺以形成非晶区域。接下来，在嵌入的SiGe层上进行源极/漏极注入工艺以形成源极掺杂区域和漏极掺杂区域。之后，进行源极/漏极退火处理以在衬底中形成源极和漏极。前非晶化植入程序和源极/漏极注入程序中的至少一个在低于-30℃的低温过程中进行。

10. 发明授权

US08324059B2 Method of fabricating a semiconductor structure 有权
标题翻译：制造半导体结构的方法
公开(公告)号：US08324059B2
公开(公告)日：2012-12-04
申请号：US13092990
申请日：2011-04-25
申请人： Ted Ming-Lang Guo , Chin-Cheng Chien , Shu-Yen Chan , Chan-Lon Yang , Chun-Yuan Wu
发明人： Ted Ming-Lang Guo , Chin-Cheng Chien , Shu-Yen Chan , Chan-Lon Yang , Chun-Yuan Wu
IPC分类号： H01L21/336
CPC分类号： H01L29/66636 , H01L21/324 , H01L29/165 , H01L29/665 , H01L29/7834
摘要： A method of fabricating a semiconductor structure, in which after an etching process is performed to form at least one recess within a semiconductor beside a gate structure, a thermal treatment is performed on the recess in a gas atmosphere including an inert gas before a silicon-containing epitaxial layer is formed in the recess through an epitaxy growth process.
摘要翻译：一种制造半导体结构的方法，其中在进行蚀刻处理以在栅极结构之外的半导体内形成至少一个凹槽时，在包含惰性气体的气体气氛中的凹部上进行热处理，通过外延生长工艺在凹部中形成含有外延层的外延层。

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