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1. 发明授权

US4416010A Double error correcting system in digital signal reproducing apparatus 失效
标题翻译：数字信号再现装置中的双纠错系统
公开(公告)号：US4416010A
公开(公告)日：1983-11-15
申请号：US254053
申请日：1981-04-14
申请人： Chitoshi Hibino , Harukuni Kobari , Susumu Suzuki , Yasuhiro Yamada
发明人： Chitoshi Hibino , Harukuni Kobari , Susumu Suzuki , Yasuhiro Yamada
IPC分类号： G11B20/18 , G06F11/10
CPC分类号： G11B20/1809
摘要： A double error correcting system is used in a digital signal reproducing apparatus, which is capable of correcting errors in two information vectors (information words) among a plurality of information vectors within one block by use of elements in a small number of correcting matrices and by using a memory device having a small memory capacity. A register is not required for temporarily storing the operational result obtained half-way between a plurality of performed operations. Instead, corrected information vectors are obtained from a memory circuit.
摘要翻译：一种双重纠错系统被用在数字信号再现装置中，该装置能够通过使用少量的校正矩阵中的元素和通过使用少量校正矩阵中的元素来校正一个块内的多个信息向量中的两个信息向量（信息字）中的错误使用具有小存储容量的存储器件。不需要寄存器来临时存储在多个执行操作之间中途获得的操作结果。相反，从存储器电路获得校正的信息向量。

2. 发明授权

US4445216A System for defeating erroneous correction in a digital signal reproducing apparatus 失效
标题翻译：用于在数字信号再现装置中消除错误校正的系统
公开(公告)号：US4445216A
公开(公告)日：1984-04-24
申请号：US242293
申请日：1981-03-10
申请人： Harukuni Kobari , Yasuhiro Yamada , Susumu Suzuki , Chitoshi Hibino
发明人： Harukuni Kobari , Yasuhiro Yamada , Susumu Suzuki , Chitoshi Hibino
IPC分类号： G11B20/18 , H03M13/00 , H03M13/27 , G06F11/10
CPC分类号： G11B20/1809
摘要： A system for defeating erroneous correction in a digital signal reproducing apparatus. The system includes a reproducing circuit for reproducing a signal sequence in which information words and error correcting words are interleaved. A memory stores the reproduced digital signal sequence and produces a digital signal sequence made up of the information words and error correcting words, which are then de-interleaved and arranged in an original sequence. A correcting circuit corrects adjacent errors with respect to the digital signal sequence produced from the memory. A digital-to-analog converter converts a digital information signal obtained from the correcting circuit into an original analog information signal. The correcting circuit calculates partial syndromes according to predetermined equations and detects the number of erroneous words in one block which is made up of interleaved words. The error correcting operation is stopped when there are certain set of conditions which are related to the values of the partial syndromes and when the number of erroneous words are satisfied. The system continues to stop the correcting operation until other sets of conditions are satisfied, in order to correct errors of up to two words in each of the blocks made up of the de-interleaved words.
摘要翻译：一种用于消除数字信号再现装置中的错误校正的系统。该系统包括用于再现其中信息字和纠错字被交错的信号序列的再现电路。存储器存储再现的数字信号序列，并产生由信息字和纠错字组成的数字信号序列，然后以原始顺序进行解交织和排列。校正电路相对于从存储器产生的数字信号序列校正相邻误差。数模转换器将从校正电路获得的数字信息信号转换为原始模拟信息信号。校正电路根据预定的方程式计算部分校正子，并检测由交错字组成的一个块中的错误字数。当存在与部分综合征的值相关的某些条件集合以及满足错误字数时，停止纠错操作。系统继续停止校正操作，直到满足其他条件为止，以便校正由解交错字组成的每个块中最多两个字的错误。

3. 发明授权

US4333160A Memory control system 失效
标题翻译：内存控制系统
公开(公告)号：US4333160A
公开(公告)日：1982-06-01
申请号：US95553
申请日：1979-11-19
申请人： Harukuni Kobari , Yasuhiro Yamada , Susumu Suzuki , Chitoshi Hibino
发明人： Harukuni Kobari , Yasuhiro Yamada , Susumu Suzuki , Chitoshi Hibino
IPC分类号： G11B20/18 , H04N5/76 , G06F13/00
CPC分类号： G11B20/1809
摘要： A memory control system comprises a first memory supplied with an incoming modulated digital signal which is formed by subjecting an analog signal to digital signal processing of discontinuous level modulation system, and a first control circuit for supplying a control signal to the first memory. The first control circuit producing the control signal for controlling the first memory in such a manner that the total memory capacity of the first memory is partitioned into a plurality (k) of memory capacity segments having given capacity values (lengths) for use, and the modulated digital signal is written in and further the modulated digital signal thus written in is read out with the order thereof rearranged, interrelatedly with the circulation of addresses through the plurality of divided memory capacity segments while maintaining constant the relationship in terms of capacity values (lengths) between the plurality of divided memory capacity segments.
摘要翻译：存储器控制系统包括：第一存储器，其被提供有通过对模拟信号进行不连续电平调制系统的数字信号处理而形成的输入调制数字信号;以及第一控制电路，用于向第一存储器提供控制信号。第一控制电路产生用于控制第一存储器的控制信号，使得第一存储器的总存储器容量被划分为具有给定容量值（长度）的多个（k）个存储容量段，并且被调制的数字信号被写入，并且进一步地读出这样写入的调制数字信号，其顺序被重新排列，与通过多个划分的存储器容量段的地址的循环相关联，同时保持在容量值（长度）上的恒定关系）在多个划分的存储器容量段之间。

4. 发明授权

US4420775A Circuit and method for protecting a horizontal synchronous signal 失效
标题翻译：用于保护水平同步信号的电路和方法
公开(公告)号：US4420775A
公开(公告)日：1983-12-13
申请号：US305779
申请日：1981-09-25
申请人： Shigeru Yamazaki , Takao Arai , Masaharu Kobayashi , Takashi Hoshino , Chitoshi Hibino , Harukuni Kobari
发明人： Shigeru Yamazaki , Takao Arai , Masaharu Kobayashi , Takashi Hoshino , Chitoshi Hibino , Harukuni Kobari
IPC分类号： H03K5/19 , H04N5/932 , H04N5/945 , G11B27/10 , G11B5/43
CPC分类号： H04N5/945 , H03K5/19 , H04N5/932
摘要： A circuit for protecting a horizontal synchronous signal comprises a horizontal synchronous signal detecting circuit responsive to horizontal synchronous pulses included in a composite synchronous signal of a reproduced PCM signal, first and second horizontal synchronous pulse supplementing or adding circuits and an output switching circuit. The output switching circuit operates so that the first supplementing circuit delivers a first supplementary pulse in the absence of a single pulse of the original horizontal synchronous signal, and the second supplementing circuit produces one or more second supplementary pulses in the absence of a plurality of continuous pulses of the original horizontal synchronous signal. When the circuit returns to a condition in which produced horizontal synchronous pulses are synchronous with the original horizontal synchronous pulses, the time interval between adjacent pulses of the original pulses is detected to see whether the interval is either longer or shorter than a predetermined value. As a result, when a pulse first appeared after the returning point is within the predetermined interval, that pulse is removed so that the number of output horizontal synchronous pulses is correct.
摘要翻译：用于保护水平同步信号的电路包括水平同步信号检测电路，其响应包括在再现的PCM信号的复合同步信号中的水平同步脉冲，第一和第二水平同步脉冲补充或加法电路以及输出切换电路。输出切换电路操作，使得第一补充电路在没有原始水平同步信号的单个脉冲的情况下传送第一辅助脉冲，并且第二补充电路在没有多个连续的情况下产生一个或多个第二辅助脉冲原始水平同步信号的脉冲。当电路返回到产生的水平同步脉冲与原始水平同步脉冲同步的状态时，检测原始脉冲的相邻脉冲之间的时间间隔，以查看间隔是否比预定值更长或更短。结果，当在返回点之后首先出现脉冲在预定间隔内时，该脉冲被去除，使得输出水平同步脉冲的数量是正确的。

5. 发明授权

US4604658A Memory control circuit for removing jitter 失效
标题翻译：用于消除抖动的存储器控制电路
公开(公告)号：US4604658A
公开(公告)日：1986-08-05
申请号：US662535
申请日：1984-10-19
申请人： Chitoshi Hibino , Harukuni Kobari
发明人： Chitoshi Hibino , Harukuni Kobari
IPC分类号： G11B20/10 , H04N5/78
CPC分类号： G11B20/10527
摘要： A random access memory has: upper and lower address limits, an address input responsive to an address counter, a write enable input, a read enable input, a data input bus, and data output bus. The address counter is supplied with a synchronization signal having a frequency determined by the frequency of a variable frequency data source. A signal having first, second and third values, respectively indicative of the address input of the memory being at the upper limit for the memory address, the lower limit for the memory address and between the upper and lower limits, is derived in response to the count in the address counter. First, second and third oscillators respectively derive first, second and third fixed frequencies such that the third frequency is greater than the second frequency and the second frequency is greater than the first frequency. The first, second and third fixed frequencies are coupled to the address counter while the signal has the third, second and first values.
摘要翻译：随机存取存储器具有：上下地址限制，响应于地址计数器的地址输入，写使能输入，读使能输入，数据输入总线和数据输出总线。地址计数器被提供有具有由可变频率数据源的频率确定的频率的同步信号。响应于第一，第二和第三值，分别指示存储器的地址输入处于存储器地址的上限，存储器地址的下限以及上限和下限之间的信号，在地址计数器中计数。第一，第二和第三振荡器分别导出第一，第二和第三固定频率，使得第三频率大于第二频率，第二频率大于第一频率。第一，第二和第三固定频率耦合到地址计数器，而信号具有第三，第二和第一值。

6. 发明授权

US4853876A Picture producing apparatus 失效
标题翻译：图像制作装置
公开(公告)号：US4853876A
公开(公告)日：1989-08-01
申请号：US867235
申请日：1986-05-23
申请人： Chitoshi Hibino , Atsushi Arimoto , Kenji Yoshihara
发明人： Chitoshi Hibino , Atsushi Arimoto , Kenji Yoshihara
IPC分类号： G09G5/06 , G06F3/153 , G06T11/00 , G09G5/00 , G09G5/39 , H04N9/804 , H04N9/82 , H04N9/877
CPC分类号： H04N9/877 , H04N9/804 , H04N9/8244
摘要： A picture producing apparatus alternately operates in mutually different first and second time periods, so as to make access to picture information at a high speed and process the picture information in real time. In the first time period, the picture producing apparatus arranges the picture information which is transmitted into a predetermined format, detects and corrects error in the picture information and writes the picture information into a first memory, and reads picture data stored in a second memory. On the other hand, in a second time period, the picture producing apparatus reads the picture information stored in the first memory, and writes the picture data of the picture information into the second memory depending on control data of the picture information.
摘要翻译：图像产生装置在相互不同的第一和第二时间段交替地操作，以便高速访问图像信息并且实时地处理图像信息。在第一时间段中，图像产生装置布置以预定格式发送的图像信息，检测并校正图像信息中的错误，并将图像信息写入第一存储器，并读取存储在第二存储器中的图像数据。另一方面，在第二时间段中，图像产生装置读取存储在第一存储器中的图像信息，并且根据图像信息的控制数据将图像信息的图像数据写入第二存储器。

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