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1. 发明授权

US06269465B1 Error correction system in a processing agent having minimal delay 有权
标题翻译：具有最小延迟的处理代理中的纠错系统
公开(公告)号：US06269465B1
公开(公告)日：2001-07-31
申请号：US09197582
申请日：1998-11-23
申请人： David L. Hill , Chinna Prudvi , Derek T. Bachand , Paul Breuder
发明人： David L. Hill , Chinna Prudvi , Derek T. Bachand , Paul Breuder
IPC分类号： H03M1300
CPC分类号： H03M13/03
摘要： An error correction system in an agent provides an error correction in a circuit path extending from an internal cache to an output of the agent. When data errors are detected for data to be processed internally within the agent, the error correction system passes the corrupted data through the error correction circuit, and out of the agent and back into the agent. The error correction changes internal data requests into an external transaction when data errors are detected.
摘要翻译：代理中的纠错系统在从内部高速缓存延伸到代理的输出的电路中提供纠错。当检测到在代理内部要处理的数据的数据错误时，纠错系统将损坏的数据通过纠错电路，并从代理程序中传回代理。当检测到数据错误时，错误修正将内部数据请求更改为外部事务。

2. 发明申请

US20100037027A1 Transaction Manager And Cache For Processing Agent 失效
标题翻译：处理代理的事务管理器和缓存
公开(公告)号：US20100037027A1
公开(公告)日：2010-02-11
申请号：US12468360
申请日：2009-05-19
申请人： Chinna Prudvi , Derek T. Bachand
发明人： Chinna Prudvi , Derek T. Bachand
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0893 , G06F12/0886
摘要： A processing agent is used in a system that transfers data of a predetermined data line length during external transactions. The agent may include an internal cache having a plurality of cache entries. Each cache entry may store multiple data line lengths of data. The agent further may include a transaction queue system having queue entries that include a primary entry including an address portion and status portion, the status portion provided for a first external transaction of the agent, and a secondary entry including a status portion provided for a second external transaction.
摘要翻译：处理代理被用于在外部事务期间传送预定数据线长度的数据的系统。代理可以包括具有多个高速缓存条目的内部高速缓存。每个缓存条目可以存储多条数据线长度的数据。代理还可以包括具有队列条目的事务队列系统，该队列条目包括包括地址部分和状态部分的主条目，为代理的第一外部事务提供的状态部分，以及包括为第二条提供的状态部分的辅助条目外部交易。

3. 发明授权

US06578114B2 Method and apparatus for altering data length to zero to maintain cache coherency 有权
公开(公告)号：US06578114B2
公开(公告)日：2003-06-10
申请号：US10180009
申请日：2002-06-26
申请人： Paul D. Breuder , Derek T. Bachand , David Lawrence Hill , Chinna Prudvi
发明人： Paul D. Breuder , Derek T. Bachand , David Lawrence Hill , Chinna Prudvi
IPC分类号： G06F1200
CPC分类号： G06F12/0831
摘要： Increased efficiency in a multiple agent system is provided by allowing all explicit writebacks to continue during a snoop phase. Upon each incoming external bus request, an agent determines if the address of that request matches an address of data within the agent. If there is a match, the agent copies this most recent data, changes the state of the data to unmodified, changes the length of the data to zero (for pending explicit writebacks), and performs an implicit writeback. Additionally, prior to each explicit writeback, an agent determines if the address of the explicit writeback and any incoming snoop request requests are the same. If there is a match, the agent changes the data length of the explicit writeback to zero prior to issuing the explicit writeback.

4. 发明授权

US06434677B1 Method and apparatus for altering data length to zero to maintain cache coherency 有权
公开(公告)号：US06434677B1
公开(公告)日：2002-08-13
申请号：US09323360
申请日：1999-06-01
申请人： Paul D. Breuder , Derek T. Bachand , David Lawrence Hill , Chinna Prudvi
发明人： Paul D. Breuder , Derek T. Bachand , David Lawrence Hill , Chinna Prudvi
IPC分类号： G06F1200
CPC分类号： G06F12/0831
摘要： Increased efficiency in a multiple agent system is provided by allowing all explicit writebacks to continue during a snoop phase. Upon each incoming external bus request, an agent determines if the address of that request matches an address of data within the agent. If there is a match, the agent copies this most recent data, changes the state of the data to unmodified, changes the length of the data to zero (for pending explicit writebacks), and performs an implicit writeback. Additionally, prior to each explicit writeback, an agent determines if the address of the explicit writeback and any incoming snoop request requests are the same. If there is a match, the agent changes the data length of the explicit writeback to zero prior to issuing the explicit writeback.

5. 发明授权

US07555603B1 Transaction manager and cache for processing agent 有权
标题翻译：处理代理的事务管理器和缓存
公开(公告)号：US07555603B1
公开(公告)日：2009-06-30
申请号：US09212291
申请日：1998-12-16
申请人： Chinna Prudvi , Derek T. Bachand
发明人： Chinna Prudvi , Derek T. Bachand
IPC分类号： G06F12/00 , G06F13/00
CPC分类号： G06F12/0893 , G06F12/0886
摘要： A processing agent is used in a system that transfers data of a predetermined data line length during external transactions. The agent may include an internal cache having a plurality of cache entries. Each cache entry may store multiple data line lengths of data. The agent further may include a transaction queue system having queue entries that include a primary entry including an address portion and status portion, the status portion provided for a first external transaction of the agent, and a secondary entry including a status portion provided for a second external transaction.
摘要翻译：处理代理被用于在外部事务期间传送预定数据线长度的数据的系统。代理可以包括具有多个高速缓存条目的内部高速缓存。每个缓存条目可以存储多条数据线长度的数据。代理还可以包括具有队列条目的事务队列系统，该队列条目包括包括地址部分和状态部分的主条目，为代理的第一外部事务提供的状态部分，以及包括为第二条提供的状态部分的辅助条目外部交易。

6. 发明授权

US06216208B1 Prefetch queue responsive to read request sequences 失效
标题翻译：预读队列响应读请求序列
公开(公告)号：US06216208B1
公开(公告)日：2001-04-10
申请号：US08999241
申请日：1997-12-29
申请人： Robert Greiner , David L. Hill , Chinna Prudvi , Derek T. Bachand , Matthew A. Fisch
发明人： Robert Greiner , David L. Hill , Chinna Prudvi , Derek T. Bachand , Matthew A. Fisch
IPC分类号： G05F1208
CPC分类号： G06F9/383 , G06F12/0862 , G06F2212/6026
摘要： A prefetching control system provided for a processor. The prefetching queue may include an arbiter, a cache queue and a prefetch queue. The arbiter issues requests including read requests. Responsive to a read request, the cache queue issues a control signal. The prefetch queue receives the control signal and an address associated with the read request. When the received address is a member of a pattern of read requests from sequential memory locations, the prefetch queue issues a prefetch request to the arbiter.
摘要翻译：为处理器提供的预取控制系统。预取队列可以包括仲裁器，高速缓存队列和预取队列。仲裁器发出请求，包括读取请求。响应于读取请求，缓存队列发出控制信号。预取队列接收控制信号和与读取请求相关联的地址。当接收到的地址是来自顺序存储器位置的读取请求的模式的成员时，预取队列向仲裁器发出预取请求。

7. 发明授权

US06209068B1 Read line buffer and signaling protocol for processor 失效
标题翻译：用于处理器的读行缓冲器和信令协议
公开(公告)号：US06209068B1
公开(公告)日：2001-03-27
申请号：US08999242
申请日：1997-12-29
申请人： David L. Hill , Chinna Prudvi , Derek T. Bachand , Matthew A. Fisch
发明人： David L. Hill , Chinna Prudvi , Derek T. Bachand , Matthew A. Fisch
IPC分类号： G06F1216
CPC分类号： G06F12/0831
摘要： A data control method in a microprocessor is disclosed. According to the method, a request is generated on an external bus for data to be read to the processor. The requested data is read from the external bus to an intermediate memory in the processor and, thereafter, read from the intermediate memory to a destination. When the intermediate memory is full, the read of data from the external bus is stalled until the intermediate memory is no longer full. Typically, stalling is accomplished by generating a stall signal on the external bus, which may be generated during a cache coherency phase of the transaction to which the requested data relates.
摘要翻译：公开了一种微处理器中的数据控制方法。根据该方法，在外部总线上生成要向处理器读取的数据的请求。所请求的数据从外部总线读取到处理器中的中间存储器，然后从中间存储器读取到目的地。当中间存储器满时，来自外部总线的数据读取停止，直至中间存储器不再满。通常，停止是通过在外部总线上生成停止信号来实现的，该停止信号可以在所请求的数据所关联的事务的高速缓存一致性阶段期间产生。

8. 发明授权

US08122194B2 Transaction manager and cache for processing agent 失效
标题翻译：处理代理的事务管理器和缓存
公开(公告)号：US08122194B2
公开(公告)日：2012-02-21
申请号：US12468360
申请日：2009-05-19
申请人： Chinna Prudvi , Derek T. Bachand
发明人： Chinna Prudvi , Derek T. Bachand
IPC分类号： G06F12/00 , G06F13/00
CPC分类号： G06F12/0893 , G06F12/0886
摘要： A processing agent is used in a system that transfers data of a predetermined data line length during external transactions. The agent may include an internal cache having a plurality of cache entries. Each cache entry may store multiple data line lengths of data. The agent further may include a transaction queue system having queue entries that include a primary entry including an address portion and status portion, the status portion provided for a first external transaction of the agent, and a secondary entry including a status portion provided for a second external transaction.
摘要翻译：处理代理被用于在外部事务期间传送预定数据线长度的数据的系统。代理可以包括具有多个高速缓存条目的内部高速缓存。每个缓存条目可以存储多条数据线长度的数据。代理还可以包括具有队列条目的事务队列系统，该队列条目包括包括地址部分和状态部分的主条目，为代理的第一外部事务提供的状态部分，以及包括为第二条提供的状态部分的辅助条目外部交易。

9. 发明授权

US06735675B2 Method and apparatus for altering data length to zero to maintain cache coherency 失效
标题翻译：将数据长度改变为零以维持高速缓存一致性的方法和装置
公开(公告)号：US06735675B2
公开(公告)日：2004-05-11
申请号：US10346060
申请日：2003-01-17
申请人： Paul D. Breuder , Derek T. Bachand , David Lawrence Hill , Chinna Prudvi
发明人： Paul D. Breuder , Derek T. Bachand , David Lawrence Hill , Chinna Prudvi
IPC分类号： G06F1200
CPC分类号： G06F12/0831
摘要： Increased efficiency in a multiple agent system is provided by allowing all explicit writebacks to continue during a snoop phase. Upon each incoming external bus request, an agent determines if the address of that request matches an address of data within the agent. If there is a match, the agent copies this most recent data, changes the state of the data to unmodified, changes the length of the data to zero (for pending explicit writebacks), and performs an implicit writeback. Additionally, prior to each explicit writeback, an agent determines if the address of the explicit writeback and any incoming snoop request requests are the same. If there is a match, the agent changes the data length of the explicit writeback to zero prior to issuing the explicit writeback.
摘要翻译：通过允许所有显式回写在窥探阶段继续进行，从而提高了多代理系统的效率。在每个传入的外部总线请求时，代理确定该请求的地址是否匹配代理中的数据的地址。如果有匹配，代理将复制最近的数据，将数据的状态更改为未修改，将数据的长度更改为零（用于挂起的显式回写），并执行隐式的回写。另外，在每个显式回写之前，代理确定显式回写的地址和任何进入的窥探请求请求是否相同。如果存在匹配，代理将在显式回写之前将显式回写的数据长度更改为零。

10. 发明授权

US06412091B2 Error correction system in a processing agent having minimal delay 有权
标题翻译：具有最小延迟的处理代理中的纠错系统
公开(公告)号：US06412091B2
公开(公告)日：2002-06-25
申请号：US09848261
申请日：2001-05-04
申请人： David L. Hill , Chinna Prudvi , Derek T. Bachand , Paul Breuder
发明人： David L. Hill , Chinna Prudvi , Derek T. Bachand , Paul Breuder
IPC分类号： H03M1300
CPC分类号： H03M13/03
摘要： An error correction system in an agent provides an error correction in a circuit path extending from an internal cache to an output of the agent. When data errors are detected for data to be processed internally within the agent, the error correction system passes the corrupted data through the error correction circuit, and out of the agent and back into the agent. The error correction changes internal data requests into an external transaction when data errors are detected.
摘要翻译：代理中的纠错系统在从内部高速缓存延伸到代理的输出的电路中提供纠错。当检测到在代理内部要处理的数据的数据错误时，纠错系统将损坏的数据通过纠错电路，并从代理程序中传回代理。当检测到数据错误时，错误修正将内部数据请求更改为外部事务。

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