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1. 发明申请

US20070040584A1 Dual-gate dynamic logic circuit with pre-charge keeper 有权
公开(公告)号：US20070040584A1
公开(公告)日：2007-02-22
申请号：US11204401
申请日：2005-08-16
申请人： Hung Ngo , Ching-Te Chuang , Keunwoo Kim , Jente Kuang , Kevin Nowka
发明人： Hung Ngo , Ching-Te Chuang , Keunwoo Kim , Jente Kuang , Kevin Nowka
IPC分类号： H03K19/096
CPC分类号： H03K19/0963
摘要： A dynamic logic gate has an asymmetrical dual-gate PFET device for charging a dynamic node during a pre-charge phase of a clock. A logic tree evaluates the dynamic node during an evaluate phase of the clock. The front gate of the asymmetrical dual-gate PFET device is coupled to the clock signal and the back gate is coupled to the ground potential of the power supply. When the clock is a logic zero both the front gate and the back gate are biased ON and the dynamic node charges with maximum current. The clock signal transitions to a logic one during the evaluation phase of the clock turning OFF the front gate. The back gate remains ON and the asymmetrical dual-gate PFET device operates as a keeper device with a current level sufficient to counter leakage on the dynamic node.

2. 发明申请

US20070047364A1 Methods and apparatus for varying a supply voltage or reference voltage using independent control of diode voltage in asymmetrical double-gate devices 审中-公开
标题翻译：使用不对称双栅极器件中二极管电压的独立控制来改变电源电压或参考电压的方法和装置
公开(公告)号：US20070047364A1
公开(公告)日：2007-03-01
申请号：US11216666
申请日：2005-08-31
申请人： Ching-Te Chuang , Keunwoo Kim , Jente Kuang , Hung Ngo , Kevin Nowka
发明人： Ching-Te Chuang , Keunwoo Kim , Jente Kuang , Hung Ngo , Kevin Nowka
IPC分类号： G11C5/14
CPC分类号： G11C5/147 , G11C11/412 , G11C11/417
摘要： Methods and apparatus are provided for varying one or more of a supply voltage and reference voltage in an integrated circuit, using independent control of a diode voltage in an asymmetrical double-gate device. An integrated circuit is provided that is controlled by one or more of a supply voltage and a reference voltage. The integrated circuit comprises an independently controlled asymmetrical double-gate device to adjust one or more of the supply voltage and the reference voltage. The independent control may comprise, for example, a back gate bias. The independently controlled asymmetrical double-gate device may be employed in a number of applications, including voltage islands, static RAM, and to improve the power and performance of a processing unit.
摘要翻译：提供了用于在集成电路中改变电源电压和参考电压中的一个或多个的方法和装置，使用对不对称双栅极器件中的二极管电压的独立控制。提供由电源电压和参考电压中的一个或多个控制的集成电路。集成电路包括独立控制的非对称双栅极器件，用于调节电源电压和参考电压中的一个或多个。独立控制可以包括例如背栅偏置。独立控制的非对称双栅极器件可以用于包括电压岛，静态RAM在内的许多应用中，并且用于改善处理单元的功率和性能。

3. 发明申请

US20070040621A1 Voltage controlled oscillator using dual gated asymmetrical FET devices 审中-公开
标题翻译：使用双门控不对称FET器件的压控振荡器
公开(公告)号：US20070040621A1
公开(公告)日：2007-02-22
申请号：US11204412
申请日：2005-08-16
申请人： Hung Ngo , Ching-Te Chuang , Keunwoo Kim , Jente Kuang , Kevin Nowka
发明人： Hung Ngo , Ching-Te Chuang , Keunwoo Kim , Jente Kuang , Kevin Nowka
IPC分类号： H03K3/03
CPC分类号： H03K3/0315
摘要： A ring oscillator is formed using inverting stages configured from asymmetrical dual gated FET (ADG-FET) devices. The simplest form uses an odd number of CMOS inverter stages configured with an ADG-PFET and an ADG-NFET. The front gates are used as the logic inputs and are coupled to preceeding outputs from the main ring. The back gates of the ADG-PFET devices are coupled to a first control voltage and the back gates of the ADG-NFET devices are coupled to a second control voltage that is the complement of the first control voltage referenced to an off-set voltage. Other configurations of logic inverting stages using ADG-FET devices may also be used. The control voltage is varied to modulate the current level set by the logic state at the inputs coupled to the front gates.
摘要翻译：使用由不对称双门控FET（ADG-FET）器件配置的反相级形成环形振荡器。最简单的形式使用由ADG-PFET和ADG-NFET配置的奇数CMOS反相器级。前门用作逻辑输入，并连接到主环的前一个输出。 ADG-PFET器件的背栅极耦合到第一控制电压，并且ADG-NFET器件的背栅极耦合到作为基于偏移电压的第一控制电压的补码的第二控制电压。也可以使用使用ADG-FET器件的逻辑反相级的其它配置。改变控制电压以调制由耦合到前门的输入端处的逻辑状态设置的电流电平。

4. 发明申请

US20060290384A1 Independent gate control logic circuitry 失效
标题翻译：独立门控逻辑电路
公开(公告)号：US20060290384A1
公开(公告)日：2006-12-28
申请号：US11168717
申请日：2005-06-28
申请人： Ching-Te Chuang , Keunwoo Kim , Jente Kuang , Kevin Nowka
发明人： Ching-Te Chuang , Keunwoo Kim , Jente Kuang , Kevin Nowka
IPC分类号： H03K19/096
CPC分类号： H03K19/0963
摘要： A dynamic logic gate has a dynamic node pre-charged in response to a pre-charge phase of a clock signal and a logic tree with a plurality of logic inputs for evaluating the dynamic node during an evaluate phase of the clock signal in response to a Boolean combination of the logic inputs. The logic tree has a stacked configuration with at least one multi-gate FET device for coupling an intermediate node of the logic tree to the dynamic node in response to a first logic input of the plurality of logic inputs or in response to the pre-charge phase of the clock signal. The multi-gate FET device has one gate coupled to the first logic input and a second gate coupled to a complement of the clock signal used to pre-charge the dynamic node.
摘要翻译：动态逻辑门具有响应于时钟信号的预充电阶段和具有多个逻辑输入的逻辑树预充电的动态节点，用于在响应于时钟信号的时钟信号的估计阶段期间评估动态节点逻辑输入的布尔组合。逻辑树具有堆叠配置，其具有至少一个多栅极FET器件，用于响应于多个逻辑输入的第一逻辑输入或响应于预充电而将逻辑树的中间节点耦合到动态节点时钟信号的相位。多栅极FET器件具有耦合到第一逻辑输入的一个栅极和耦合到用于预充电动态节点的时钟信号的补码的第二栅极。

5. 发明申请

US20060290383A1 Dual gate dynamic logic 有权
标题翻译：双门动态逻辑
公开(公告)号：US20060290383A1
公开(公告)日：2006-12-28
申请号：US11168692
申请日：2005-06-28
申请人： Ching-Te Chuang , Keunwoo Kim , Jente Kuang , Kevin Nowka
发明人： Ching-Te Chuang , Keunwoo Kim , Jente Kuang , Kevin Nowka
IPC分类号： H03K19/096
CPC分类号： H03K19/0963
摘要： A dynamic logic gate has a device for charging a dynamic node during a pre-charge phase of a clock. A logic tree evaluates the dynamic node with a device during an evaluate phase of the clock. The dynamic node has a keeper circuit comprising an inverter with its input coupled to the dynamic node and its output coupled to the back gate of a dual gate PFET device. The source of the dual gate PFET is coupled to the power supply and its drain is coupled to the dynamic node forming a half latch. The front gate of the dual gate PFET is coupled to a logic circuit with a mode input and a logic input coupled back to a node sensing the state of the dynamic node. The mode input may be a slow mode to preserve dynamic node state or the clock delayed that turns ON the strong keeper after evaluation.
摘要翻译：动态逻辑门具有用于在时钟的预充电阶段对动态节点充电的装置。逻辑树在时钟的评估阶段使用设备来评估动态节点。动态节点具有保持器电路，其包括反相器，其输入耦合到动态节点，其输出耦合到双栅极PFET器件的背栅极。双栅极PFET的源极耦合到电源，并且其漏极耦合到形成半锁存器的动态节点。双栅极PFET的前栅极耦合到具有模式输入和逻辑输入的逻辑电路，逻辑输入耦合回到感测动态节点的状态的节点。模式输入可能是缓慢的模式，以保持动态节点状态或时钟延迟，在评估后打开强守护者。

6. 发明申请

US20070096770A1 Cascaded pass-gate test circuit with interposed split-output drive devices 失效
标题翻译：带有插入式分离输出驱动装置的级联传输门测试电路
公开(公告)号：US20070096770A1
公开(公告)日：2007-05-03
申请号：US11260571
申请日：2005-10-27
申请人： Ching-Te Chuang , Jente Kuang , Hung Ngo
发明人： Ching-Te Chuang , Jente Kuang , Hung Ngo
IPC分类号： H03K19/00
CPC分类号： G01R31/31725
摘要： A cascaded pass-gate test circuit including interposed split-output drive devices provides accurate measurement of critical timing parameters of pass gates. The rise time and fall time of signals passed through the pass gate can be separately measured in a ring oscillator or one-shot delay line configuration. Inverters or other buffer circuits are provided as drive devices to couple the pass gates in cascade. The final complementary tree in each drive device is split so that the only one of the output pull-down transistor or pull-up transistor is connected to the next pass gate input, while the other transistor is connected to the output of the pass gate. The result is that the state transition associated with the device connected to the pass gate input is dominant in the delay, while the other state transition is propagated directly to the output of the pass gate, bypassing the pass gate.
摘要翻译：包括插入式分离输出驱动装置的级联通过栅极测试电路提供对通孔的临界定时参数的精确测量。通过通过门的信号的上升时间和下降时间可以在环形振荡器或单稳态延迟线配置中单独测量。逆变器或其它缓冲电路被提供作为驱动装置来串联耦合通过门。每个驱动装置中的最终互补树被分开，使得输出下拉晶体管或上拉晶体管中的唯一一个连接到下一个通过栅极输入，而另一个晶体管连接到通过栅极的输出端。结果是，与连接到通过栅极输入的器件相关联的状态转变在延迟中是主要的，而另一个状态转变直接传播到通过栅极的输出，绕过通过栅极。

7. 发明申请

US20070046323A1 Control circuitry for power gating virtual power supply rails at differing voltage potentials 失效
公开(公告)号：US20070046323A1
公开(公告)日：2007-03-01
申请号：US11211954
申请日：2005-08-25
申请人： Jente Kuang , Hung Ngo , Kevin Nowka
发明人： Jente Kuang , Hung Ngo , Kevin Nowka
IPC分类号： H03K17/16
CPC分类号： H03K19/0016
摘要： A single-stage level shifting circuit is used to interface control signals across the boundary between voltage domains with differing positive or ground voltage potentials Asserted states are determined by the difference between the positive voltages potentials and the ground potentials. A lower positive power supply potential is not used to turn OFF PFET coupled to a higher positive power supply potential. Likewise a higher ground power supply potential is not used to turn OF NFETs coupled to a power domain where is significant ground shift. The single stage level shifting circuit has keeper devices that hold asserted states using voltages within the power gated domain.

8. 发明申请

US20070237012A1 Cascaded test circuit with inter-bitline drive devices for evaluating memory cell performance 有权
标题翻译：级联测试电路采用位线驱动器件，用于评估存储单元性能
公开(公告)号：US20070237012A1
公开(公告)日：2007-10-11
申请号：US11250061
申请日：2005-10-13
申请人： Jente Kuang , Jerry Kao , Hung Ngo , Kevin Nowka
发明人： Jente Kuang , Jerry Kao , Hung Ngo , Kevin Nowka
IPC分类号： G11C7/00
CPC分类号： G11C29/50 , G11C11/41 , G11C29/50012 , G11C2029/1204
摘要： A cascaded test circuit with inter-bitline drive devices for evaluating memory cell performance provides for circuit delay and performance measurements in an actual memory circuit environment. A row in a memory array is enabled along with a set of drive devices that couple each bitline pair to the next in complement fashion to form a cascade of memory cells. The drive devices can be inverters and the inverters can be sized to simulate the bitline read pre-charge device and the write state-forcing device so that the cascade operates under the same loading/drive conditions as the operational with memory cell read/write circuits. The last and first bitline in the row can be cascaded, providing a ring oscillator or the delay of the cascade can be measured in response to a transition introduced at the head of the cascade. Weak read and/or weak write conditions can be measured by selective loading.
摘要翻译：具有用于评估存储器单元性能的位线驱动装置的级联测试电路在实际存储器电路环境中提供电路延迟和性能测量。存储器阵列中的行与一组驱动装置一起被启用，这些驱动装置将每个位线对以互补方式耦合到下一个位置以形成级联的存储器单元。驱动装置可以是逆变器，并且逆变器的大小可以模拟位线读取预充电装置和写入状态强制装置，使得级联在与存储单元读/写电路的操作相同的加载/驱动条件下操作。该行中的最后一个和第一个位线可以级联，提供环形振荡器，或者响应于在级联头部引入的转换，可以测量级联的延迟。弱写入条件和/或弱写入条件可以通过选择性加载来测量。

9. 发明申请

US20060061388A1 Fast turn-off circuit for controlling leakage 失效
标题翻译：用于控制泄漏的快速关断电路
公开(公告)号：US20060061388A1
公开(公告)日：2006-03-23
申请号：US10948444
申请日：2004-09-23
申请人： Jente Kuang , Hung Ngo , Kevin Nowka
发明人： Jente Kuang , Hung Ngo , Kevin Nowka
IPC分类号： H03K19/094
CPC分类号： H03K19/0013 , H03K19/01721
摘要： A buffer, logic circuit, and data processing system employing fast turn-off drive circuitry for reducing leakage. Leakage current in logic circuitry is managed by coupling and decoupling the voltage potentials applied to large, high-leakage devices. Circuitry includes a low leakage logic path for holding logic states of an output after turning off high-leakage devices. A fast turn-off logic path in parallel with the low leakage logic path is used to assert each logic state in the forward direction from input to output. The large output device in each fast turn-off path is relieved of leakage stress by asserting logic states at driver inputs that cause the driver to turn OFF after the output logic state has been asserted.
摘要翻译：缓冲器，逻辑电路和数据处理系统采用快速关断驱动电路来减少泄漏。逻辑电路中的泄漏电流通过耦合和去耦合施加到大型高漏电器件的电压来进行管理。电路包括一个低泄漏逻辑路径，用于在关闭高漏电器件之后保持输出的逻辑状态。使用与低泄漏逻辑路径并行的快速关断逻辑路径来断言从输入到输出的正向的每个逻辑状态。在每个快速关闭路径中的大输出设备通过在驱动器输入端断言逻辑状态来消除泄漏应力，导致在输出逻辑状态被置位之后驱动器关闭。

10. 发明申请

US20060059376A1 Dynamic leakage control circuit 失效
标题翻译：动态泄漏控制电路
公开(公告)号：US20060059376A1
公开(公告)日：2006-03-16
申请号：US10942419
申请日：2004-09-16
申请人： Hung Ngo , Jente Kuang , Kevin Nowka , Rajiv Joshi
发明人： Hung Ngo , Jente Kuang , Kevin Nowka , Rajiv Joshi
IPC分类号： G06F1/26
CPC分类号： G06F1/3228
摘要： A low power consumption pipeline circuit architecture has power partitioned pipeline stages. The first pipeline stage is non-power-gated for fast response in processing input data after receipt of a valid data signal. A power-gated second pipeline stage has two power-gated modes. Normally the power rail in the power-gated second pipeline stage is charged to a first voltage potential of a pipeline power supply. In the first power gated mode, the power rail is charged to a threshold voltage below the first voltage potential to reduce leakage. In the second power gated mode. the power rail is decoupled from the first voltage potential. A power-gated third pipeline stage has its power rail either coupled to the first voltage potential or power-gated where its power rail is decoupled from the first voltage potential. The power rail of the second power-gated pipeline stage charges to the first voltage potential before the third power-gated pipeline stage.
摘要翻译：低功耗流水线电路架构具有电源分配管线级。第一个流水线阶段是非功率门控，用于在接收到有效的数据信号后处理输入数据的快速响应。电源门控第二管道级具有两个电源门控模式。通常，电源门控第二管线级中的电源轨被充电到管线电源的第一电压电位。在第一电源门控模式中，电力轨被充电到低于第一电压电位的阈值电压以减少泄漏。在第二电源门控模式下。电源轨与第一电压电位分离。电源门控第三管线级具有其电源轨或者耦合到第一电压电势或电源门控，其电源轨与第一电压电势分离。第二电力门控管道阶段的电力轨道在第三电力门控管道阶段之前充电到第一电压电位。

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