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1. 发明申请

US20090261937A1 INTEGRATED INDUCTOR 有权
标题翻译：集成电感器
公开(公告)号：US20090261937A1
公开(公告)日：2009-10-22
申请号：US12493245
申请日：2009-06-29
申请人： Ching-Chung Ko , Tung-Hsing Lee , Kuei-Ti Chan , Tao Cheng , Ming-Tzong Yang
发明人： Ching-Chung Ko , Tung-Hsing Lee , Kuei-Ti Chan , Tao Cheng , Ming-Tzong Yang
IPC分类号： H01F5/00
CPC分类号： H01L23/5227 , H01L28/10 , H01L2924/0002 , H01L2924/00
摘要： An integrated inductor includes a winding consisting of an aluminum layer atop a passivation layer, wherein the aluminum layer does not extend into the passivation layer and has a thickness that is not less than about 2.0 micrometers. The passivation layer has a thickness not less than about 0.8 micrometers. By eliminating copper from the integrated inductor and increasing the thickness of the passivation layer, the distance between the bottom surface of the inductor structure and the main surface of the semiconductor substrate is increased, thus the parasitic substrate coupling may be reduced and the Q-factor may be improved. Besides, the increased thickness of the aluminum layer may help improve the Q-factor as well.
摘要翻译：集成电感器包括由钝化层顶部的铝层组成的绕组，其中铝层不延伸到钝化层中，并且具有不小于约2.0微米的厚度。钝化层的厚度不小于约0.8微米。通过从集成电感器中消除铜并增加钝化层的厚度，电感器结构的底表面与半导体衬底的主表面之间的距离增加，因此寄生衬底耦合可能会降低，Q因子可以改进。此外，铝层的增加的厚度也可以有助于改善Q因子。

2. 发明授权

US08860544B2 Integrated inductor 有权
标题翻译：集成电感
公开(公告)号：US08860544B2
公开(公告)日：2014-10-14
申请号：US12493245
申请日：2009-06-29
申请人： Ching-Chung Ko , Tung-Hsing Lee , Kuei-Ti Chan , Tao Cheng , Ming-Tzong Yang
发明人： Ching-Chung Ko , Tung-Hsing Lee , Kuei-Ti Chan , Tao Cheng , Ming-Tzong Yang
IPC分类号： H01F5/00
CPC分类号： H01L23/5227 , H01L28/10 , H01L2924/0002 , H01L2924/00
摘要： An integrated inductor includes a winding consisting of an aluminum layer atop a passivation layer, wherein the aluminum layer does not extend into the passivation layer and has a thickness that is not less than about 2.0 micrometers. The passivation layer has a thickness not less than about 0.8 micrometers. By eliminating copper from the integrated inductor and increasing the thickness of the passivation layer, the distance between the bottom surface of the inductor structure and the main surface of the semiconductor substrate is increased, thus the parasitic substrate coupling may be reduced and the Q-factor may be improved. Besides, the increased thickness of the aluminum layer may help improve the Q-factor as well.
摘要翻译：集成电感器包括由钝化层顶部的铝层组成的绕组，其中铝层不延伸到钝化层中，并且具有不小于约2.0微米的厚度。钝化层的厚度不小于约0.8微米。通过从集成电感器中消除铜并增加钝化层的厚度，电感器结构的底表面与半导体衬底的主表面之间的距离增加，因此寄生衬底耦合可能会降低，Q因子可以改进。此外，铝层的增加的厚度也可以有助于改善Q因子。

3. 发明授权

US07897995B2 Lateral bipolar junction transistor with reduced base resistance 有权
标题翻译：具有降低的基极电阻的横向双极结晶体管
公开(公告)号：US07897995B2
公开(公告)日：2011-03-01
申请号：US12420046
申请日：2009-04-07
申请人： Ming-Tzong Yang , Tao Cheng , Ching-Chung Ko , Tung-Hsing Lee
发明人： Ming-Tzong Yang , Tao Cheng , Ching-Chung Ko , Tung-Hsing Lee
IPC分类号： H01L29/735
CPC分类号： H01L29/735 , H01L29/0692 , H01L29/423
摘要： A lateral bipolar junction transistor formed in a semiconductor substrate includes an emitter region; a base region surrounding the emitter region; a gate disposed at least over a portion of the base region; a collector region having at least one open side and being disposed about a periphery of the base region; a shallow trench isolation (STI) region disposed about a periphery of the collector region; a base contact region disposed about a periphery of the STI region; and an extension region merging with the base contact region and laterally extending to the gate on the open side of the collector region.
摘要翻译：形成在半导体衬底中的横向双极结型晶体管包括发射极区域; 围绕发射极区域的基极区域; 设置在所述基部区域的至少一部分上的栅极; 具有至少一个开放侧并且围绕所述基底区域的周边设置的收集器区域; 设置在集电极区域周围的浅沟槽隔离（STI）区域; 设置在所述STI区域周围的基极接触区域; 以及与所述基极接触区域合并并横向延伸到所述集电极区域的开放侧的栅极的延伸区域。

4. 发明授权

US07671469B2 SiGe device with SiGe-embedded dummy pattern for alleviating micro-loading effect 有权
标题翻译： SiGe器件采用SiGe嵌入式虚拟图案，可减轻微负载效应
公开(公告)号：US07671469B2
公开(公告)日：2010-03-02
申请号：US11967264
申请日：2007-12-31
申请人： Tung-Hsing Lee , Ming-Tzong Yang , Tao Cheng , Ching-Chung Ko , Tien-Chang Chang , Yu-Tung Chang
发明人： Tung-Hsing Lee , Ming-Tzong Yang , Tao Cheng , Ching-Chung Ko , Tien-Chang Chang , Yu-Tung Chang
IPC分类号： H01L23/52
CPC分类号： H01L29/7848 , H01L21/02532 , H01L21/02658 , H01L21/823412 , H01L21/823418 , H01L29/165 , H01L29/66628 , H01L29/66636
摘要： A semiconductor device with dummy patterns for alleviating micro-loading effect includes a semiconductor substrate having thereon a middle annular region between an inner region and an outer region; a SiGe device on the semiconductor substrate within the inner region; and a plurality of dummy patterns provided on the semiconductor substrate within the middle annular region. At least one of the dummy patterns contains SiGe.
摘要翻译：具有用于减轻微负载效应的虚设图形的半导体器件包括其内部区域和外部区域之间具有中间环形区域的半导体衬底; 内部区域中的半导体衬底上的SiGe器件; 以及设置在中间环形区域内的半导体衬底上的多个虚设图案。至少一个虚拟图案包含SiGe。

5. 发明申请

US20090166676A1 SIGE DEVICE WITH SIGE-EMBEDDED DUMMY PATTERN FOR ALLEVIATING MICRO-LOADING EFFECT 有权
标题翻译：具有用于识别微载荷效应的信号嵌入式模式的信号装置
公开(公告)号：US20090166676A1
公开(公告)日：2009-07-02
申请号：US11967264
申请日：2007-12-31
申请人： Tung-Hsing Lee , Ming-Tzong Yang , Tao Cheng , Ching-Chung Ko , Tien-Chang Chang , Yu-Tung Chang
发明人： Tung-Hsing Lee , Ming-Tzong Yang , Tao Cheng , Ching-Chung Ko , Tien-Chang Chang , Yu-Tung Chang
IPC分类号： H01L29/78
CPC分类号： H01L29/7848 , H01L21/02532 , H01L21/02658 , H01L21/823412 , H01L21/823418 , H01L29/165 , H01L29/66628 , H01L29/66636
摘要： A semiconductor device with dummy patterns for alleviating micro-loading effect includes a semiconductor substrate having thereon a middle annular region between an inner region and an outer region; a SiGe device on the semiconductor substrate within the inner region; and a plurality of dummy patterns provided on the semiconductor substrate within the middle annular region. At least one of the dummy patterns contains SiGe.
摘要翻译：具有用于减轻微负载效应的虚设图形的半导体器件包括其内部区域和外部区域之间具有中间环形区域的半导体衬底; 内部区域中的半导体衬底上的SiGe器件; 以及设置在中间环形区域内的半导体衬底上的多个虚设图案。至少一个虚拟图案包含SiGe。

6. 发明申请

US20100252860A1 LATERAL BIPOLAR JUNCTION TRANSISTOR WITH REDUCED BASE RESISTANCE 有权
标题翻译：具有降低基极电阻的侧向双极晶体管
公开(公告)号：US20100252860A1
公开(公告)日：2010-10-07
申请号：US12420046
申请日：2009-04-07
申请人： Ming-Tzong Yang , Tao Cheng , Ching-Chung Ko , Tung-Hsing Lee
发明人： Ming-Tzong Yang , Tao Cheng , Ching-Chung Ko , Tung-Hsing Lee
IPC分类号： H01L29/735
CPC分类号： H01L29/735 , H01L29/0692 , H01L29/423
摘要： A lateral bipolar junction transistor formed in a semiconductor substrate includes an emitter region; a base region surrounding the emitter region; a gate disposed at least over a portion of the base region; a collector region having at least one open side and being disposed about a periphery of the base region; a shallow trench isolation (STI) region disposed about a periphery of the collector region; a base contact region disposed about a periphery of the STI region; and an extension region merging with the base contact region and laterally extending to the gate on the open side of the collector region.
摘要翻译：形成在半导体衬底中的横向双极结型晶体管包括发射极区域; 围绕发射极区域的基极区域; 设置在所述基部区域的至少一部分上的栅极; 具有至少一个开放侧并且围绕所述基底区域的周边设置的收集器区域; 设置在集电极区域周围的浅沟槽隔离（STI）区域; 设置在所述STI区域周围的基极接触区域; 以及与所述基极接触区域合并并横向延伸到所述集电极区域的开放侧的栅极的延伸区域。

7. 发明申请

US20130002375A1 TRANSMISSION LINE STRUCTURE WITH LOW CROSSTALK 审中-公开
标题翻译：传动线结构与低CROSSTALK
公开(公告)号：US20130002375A1
公开(公告)日：2013-01-03
申请号：US13175253
申请日：2011-07-01
申请人： Ming-Tzong Yang , Tung-Hsing Lee , Kuei-Ti Chan
发明人： Ming-Tzong Yang , Tung-Hsing Lee , Kuei-Ti Chan
IPC分类号： H01P3/08
CPC分类号： H01L23/5225 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： A transmission line structure is disclosed. The structure includes at least one signal transmission line and a pair of ground transmission lines embedded in a first level of a dielectric layer on a substrate, wherein the pair of ground transmission lines are on both sides of the signal transmission line. A first ground layer is embedded in a second level lower than the first level of the dielectric layer and a second ground layer is embedded in a third level higher than the first level of the dielectric layer. First and second pairs of via connectors are embedded in the dielectric layer, wherein the first pair of via connectors electrically connects the pair of ground transmission lines to the first ground layer and the second pair of via connectors electrically connects the pair of ground transmission lines to the second ground layer.
摘要翻译：公开了传输线结构。该结构包括至少一个信号传输线和嵌入在基板上的电介质层的第一层中的一对接地传输线，其中该对接地传输线位于信号传输线的两侧。第一接地层嵌入在比电介质层的第一电平低的第二电平中，并且第二接地层嵌入在比电介质层的第一电平高的第三电平中。第一对和第二对通孔连接器嵌入在电介质层中，其中第一对通孔连接器将一对接地传输线电连接到第一接地层，而第二对通孔连接器将一对接地传输线电连接到第二层地层。

8. 发明申请

US20090002114A1 INTEGRATED INDUCTOR 审中-公开
标题翻译：集成电感器
公开(公告)号：US20090002114A1
公开(公告)日：2009-01-01
申请号：US11768199
申请日：2007-06-26
申请人： Ming-Tzong Yang , Kuei-Ti Chan , Ching-Chung Ko
发明人： Ming-Tzong Yang , Kuei-Ti Chan , Ching-Chung Ko
IPC分类号： H01F5/00
CPC分类号： H01L23/5227 , H01L28/10 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： An integrated inductor has a winding. The winding includes a first level metal layer inlaid in a first dielectric layer, a second level metal layer inlaid in a second dielectric layer above the first dielectric layer, and a first line-shaped via structure inlaid in a slot of a third dielectric layer interposed between the first and second dielectric layers for interconnecting the first and second level metal layers.
摘要翻译：集成电感器具有绕组。绕组包括镶嵌在第一介电层中的第一层金属层，镶嵌在第一介电层上方的第二介电层中的第二层金属层，以及镶嵌在第三介电层的槽中的第一线状通孔结构，在第一和第二电介质层之间，用于互连第一和第二层金属层。

9. 发明授权

US07932581B2 Lateral bipolar junction transistor 有权
标题翻译：侧面双极结晶体管
公开(公告)号：US07932581B2
公开(公告)日：2011-04-26
申请号：US12464107
申请日：2009-05-12
申请人： Ming-Tzong Yang , Ching-Chung Ko , Tung-Hsing Lee , Zheng Zeng
发明人： Ming-Tzong Yang , Ching-Chung Ko , Tung-Hsing Lee , Zheng Zeng
IPC分类号： H01L29/66
CPC分类号： H01L29/735 , H01L21/8249 , H01L27/0623 , H01L29/0692 , H01L29/6625
摘要： A lateral bipolar junction transistor includes an emitter region; a base region surrounding the emitter region; a gate disposed at least over a portion of the base region; a collector region surrounding the base region with an offset between an edge of the gate and the collector region; a lightly doped drain region between the edge of the gate and the collector region; a salicide block layer disposed on or over the lightly doped drain region; and a collector salicide formed on at least a portion of the collector region.
摘要翻译：横向双极结晶体管包括发射极区域; 围绕发射极区域的基极区域; 设置在所述基部区域的至少一部分上的栅极; 集电极区域，围绕所述基极区域，在所述栅极的边缘和所述集电极区域之间具有偏移; 在栅极的边缘和集电极区域之间的轻掺杂漏极区; 设置在所述轻掺杂漏极区域上或上部的自对准硅化物阻挡层; 以及形成在所述收集器区域的至少一部分上的收集器自对准硅化物。

10. 发明申请

US20090215277A1 DUAL CONTACT ETCH STOP LAYER PROCESS 审中-公开
标题翻译：双重接触蚀刻停止层工艺
公开(公告)号：US20090215277A1
公开(公告)日：2009-08-27
申请号：US12037089
申请日：2008-02-26
申请人： Tung-Hsing Lee , Ming-Tzong Yang , Ching-Chung Ko , Tien-Chang Chang , Yu-Tung Chang
发明人： Tung-Hsing Lee , Ming-Tzong Yang , Ching-Chung Ko , Tien-Chang Chang , Yu-Tung Chang
IPC分类号： H01L21/31
CPC分类号： H01L21/823807 , H01L21/823871 , H01L29/7843
摘要： A dual CESL process includes: (1) providing a substrate having thereon a first device region, a second device region and a shallow trench isolation (STI) region between the first and second device regions; (2) forming a first-stress imparting film with a first stress over the substrate, wherein the first-stress imparting film does not cover the second device region; and (3) forming a second-stress imparting film with a second stress over the substrate, wherein the second-stress imparting film does not cover the first device region, an overlapped boundary between the first- and second-stress imparting films is created directly above the STI region, and wherein the overlapped boundary is placed in close proximity to the second device region in order to induce the first stress to a channel region thereof in a transversal direction.
摘要翻译：双CESL工艺包括：（1）提供其上具有第一和第二器件区域之间的第一器件区域，第二器件区域和浅沟槽隔离（STI）区域的衬底; （2）在所述基板上形成具有第一应力的第一应力赋予膜，其中所述第一应力赋予膜不覆盖所述第二器件区域; 和（3）在基板上形成具有第二应力的第二应力赋予膜，其中第二应力赋予膜不覆盖第一器件区域，直接产生第一和第二施加应力膜之间的重叠边界在STI区域之上，并且其中重叠的边界被放置成紧邻第二器件区域，以便在横向方向上引起其沟道区域的第一应力。

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