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1. 发明授权

US07335982B2 Chip package structure and chip packaging process 有权
标题翻译：芯片封装结构和芯片封装工艺
公开(公告)号：US07335982B2
公开(公告)日：2008-02-26
申请号：US10907340
申请日：2005-03-30
申请人： Chin-Li Kao , Yi-Shao Lai , Jeng-Da Wu , Tong-Hong Wang
发明人： Chin-Li Kao , Yi-Shao Lai , Jeng-Da Wu , Tong-Hong Wang
IPC分类号： H01L23/10
CPC分类号： H01L23/36 , H01L23/13 , H01L23/3128 , H01L24/48 , H01L24/73 , H01L2224/32245 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2924/00014 , H01L2924/12042 , H01L2924/14 , H01L2924/15153 , H01L2924/1517 , H01L2924/15311 , H01L2924/1532 , H01L2924/181 , H01L2924/00012 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A chip packaging process is provided. First, a cavity is formed on a heat sink. A first encapsulant is formed on the bottom of the cavity. A circuit substrate is disposed over the heat sink. The circuit substrate has an opening that corresponds in position to the cavity. Thereafter, a chip is disposed on the first encapsulant and the chip is electrically connected to the circuit substrate. Finally, a compound is deposited over the first encapsulant and the chip to form a chip package. The chip package is warp resistant and the chip packaging process increases overall production yield.
摘要翻译：提供了芯片封装工艺。首先，在散热器上形成空腔。第一密封剂形成在空腔的底部。电路基板设置在散热器的上方。电路基板具有与空腔相对应的开口。此后，芯片设置在第一密封剂上，并且芯片电连接到电路基板。最后，化合物沉积在第一密封剂和芯片上以形成芯片封装。芯片封装具有抗扭性，芯片封装工艺提高了整体生产成本。

2. 发明申请

US20050224956A1 CHIP PACKAGE STRUCTURE AND CHIP PACKAGING PROCESS 有权
标题翻译：芯片包装结构和芯片包装过程
公开(公告)号：US20050224956A1
公开(公告)日：2005-10-13
申请号：US10907340
申请日：2005-03-30
申请人： Chin-Li Kao , Yi-Shao Lai , Jeng-Da Wu , Tong-Hong Wang
发明人： Chin-Li Kao , Yi-Shao Lai , Jeng-Da Wu , Tong-Hong Wang
IPC分类号： H01L23/10 , H01L23/13 , H01L23/28 , H01L23/31 , H01L23/36
CPC分类号： H01L23/36 , H01L23/13 , H01L23/3128 , H01L24/48 , H01L24/73 , H01L2224/32245 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2924/00014 , H01L2924/12042 , H01L2924/14 , H01L2924/15153 , H01L2924/1517 , H01L2924/15311 , H01L2924/1532 , H01L2924/181 , H01L2924/00012 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A chip packaging process is provided. First, a cavity is formed on a heat sink. A first encapsulant is formed on the bottom of the cavity. A circuit substrate is disposed over the heat sink. The circuit substrate has an opening that corresponds in position to the cavity. Thereafter, a chip is disposed on the first encapsulant and the chip is electrically connected to the circuit substrate. Finally, a compound is deposited over the first encapsulant and the chip to form a chip package. The chip package is warp resistant and the chip packaging process increases overall production yield.
摘要翻译：提供了芯片封装工艺。首先，在散热器上形成空腔。第一密封剂形成在空腔的底部。电路基板设置在散热器的上方。电路基板具有与空腔相对应的开口。此后，芯片设置在第一密封剂上，并且芯片电连接到电路基板。最后，化合物沉积在第一密封剂和芯片上以形成芯片封装。芯片封装具有抗扭性，芯片封装工艺提高了整体生产成本。

3. 发明授权

US07482204B2 Chip packaging process 有权
标题翻译：芯片封装工艺
公开(公告)号：US07482204B2
公开(公告)日：2009-01-27
申请号：US11962109
申请日：2007-12-21
申请人： Chin-Li Kao , Yi-Shao Lai , Jeng-Da Wu , Tong-Hong Wang
发明人： Chin-Li Kao , Yi-Shao Lai , Jeng-Da Wu , Tong-Hong Wang
IPC分类号： H01L21/44
CPC分类号： H01L23/36 , H01L23/13 , H01L23/3128 , H01L24/48 , H01L24/73 , H01L2224/32245 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2924/00014 , H01L2924/12042 , H01L2924/14 , H01L2924/15153 , H01L2924/1517 , H01L2924/15311 , H01L2924/1532 , H01L2924/181 , H01L2924/00012 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A chip packaging process is provided. First, a cavity is formed on a heat sink. A first encapsulant is formed on the bottom of the cavity. A circuit substrate is disposed over the heat sink. The circuit substrate has an opening that corresponds in position to the cavity. Thereafter, a chip is disposed on the first encapsulant and the chip is electrically connected to the circuit substrate. Finally, a compound is deposited over the first encapsulant and the chip to form a chip package. The chip package is warp resistant and the chip packaging process increases overall production yield.
摘要翻译：提供了芯片封装工艺。首先，在散热器上形成空腔。第一密封剂形成在空腔的底部。电路基板设置在散热器的上方。电路基板具有与空腔相对应的开口。此后，芯片设置在第一密封剂上，并且芯片电连接到电路基板。最后，化合物沉积在第一密封剂和芯片上以形成芯片封装。芯片封装具有抗扭性，芯片封装工艺提高了整体生产成本。

4. 发明申请

US20080096325A1 CHIP PACKAGING PROCESS 有权
标题翻译：芯片包装工艺
公开(公告)号：US20080096325A1
公开(公告)日：2008-04-24
申请号：US11962109
申请日：2007-12-21
申请人： Chin-Li Kao , Yi-Shao Lai , Jeng-Da Wu , Tong-Hong Wang
发明人： Chin-Li Kao , Yi-Shao Lai , Jeng-Da Wu , Tong-Hong Wang
IPC分类号： H01L21/56
CPC分类号： H01L23/36 , H01L23/13 , H01L23/3128 , H01L24/48 , H01L24/73 , H01L2224/32245 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2924/00014 , H01L2924/12042 , H01L2924/14 , H01L2924/15153 , H01L2924/1517 , H01L2924/15311 , H01L2924/1532 , H01L2924/181 , H01L2924/00012 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A chip packaging process is provided. First, a cavity is formed on a heat sink. A first encapsulant is formed on the bottom of the cavity. A circuit substrate is disposed over the heat sink. The circuit substrate has an opening that corresponds in position to the cavity. Thereafter, a chip is disposed on the first encapsulant and the chip is electrically connected to the circuit substrate. Finally, a compound is deposited over the first encapsulant and the chip to form a chip package. The chip package is warp resistant and the chip packaging process increases overall production yield.
摘要翻译：提供了芯片封装工艺。首先，在散热器上形成空腔。第一密封剂形成在空腔的底部。电路基板设置在散热器的上方。电路基板具有与空腔相对应的开口。此后，芯片设置在第一密封剂上，并且芯片电连接到电路基板。最后，化合物沉积在第一密封剂和芯片上以形成芯片封装。芯片封装具有抗扭性，芯片封装工艺提高了整体生产成本。

5. 发明申请

US20050263883A1 Asymmetric bump structure 审中-公开
标题翻译：不对称凸块结构
公开(公告)号：US20050263883A1
公开(公告)日：2005-12-01
申请号：US11134223
申请日：2005-05-20
申请人： Tong-Hong Wang , Yi-Shao Lai , Jeng-Da Wu
发明人： Tong-Hong Wang , Yi-Shao Lai , Jeng-Da Wu
IPC分类号： H01L23/48 , H01L23/485
CPC分类号： H01L24/05 , H01L24/13 , H01L2224/0401 , H01L2224/05555 , H01L2224/13027 , H01L2224/13099 , H01L2924/01013 , H01L2924/01015 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/00014
摘要： An asymmetric bump structure for wafer is provided. First, the wafer includes multi-chip units each of which has an active surface. The asymmetric bump structure includes a conductive surface on the active surface, a conductive structure contacted the portion of the conductive surface and located on the both conductive surface and the active surface, and a conductive material contacted the conductive structure. The conductive material and the conductive structure contacted part of the conductive surface have respective geometric centers which are not on an identical vertical axis.
摘要翻译：提供了一种用于晶片的不对称凸块结构。首先，晶片包括各自具有活性表面的多芯片单元。不对称凸块结构包括在有源表面上的导电表面，导电结构接触导电表面的部分并且位于导电表面和有源表面上，导电材料与导电结构接触。导电材料和与导电表面接触的部分的导电结构具有不在相同垂直轴上的相应几何中心。

6. 发明申请

US20070145604A1 CHIP STRUCTURE AND CHIP MANUFACTURING PROCESS 审中-公开
标题翻译：芯片结构和芯片制造工艺
公开(公告)号：US20070145604A1
公开(公告)日：2007-06-28
申请号：US11610319
申请日：2006-12-13
申请人： Chin-Li Kao , Tong-Hong Wang , Yi-Shao Lai
发明人： Chin-Li Kao , Tong-Hong Wang , Yi-Shao Lai
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L24/11 , H01L24/13 , H01L2224/05001 , H01L2224/05022 , H01L2224/05027 , H01L2224/05124 , H01L2224/05147 , H01L2224/05166 , H01L2224/05572 , H01L2224/05647 , H01L2224/05655 , H01L2224/05666 , H01L2224/11 , H01L2224/1132 , H01L2224/1147 , H01L2224/13 , H01L2224/13111 , H01L2224/13144 , H01L2224/16 , H01L2924/00013 , H01L2924/01013 , H01L2924/01022 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01079 , H01L2924/14 , H01L2924/00014 , H01L2224/13099 , H01L2924/00
摘要： A chip manufacturing process is disclosed. A wafer having a passivation layer and at least one bonding pad is provided. The surface of the bonding pad is exposed to a first opening of the passivation layer. A first metal layer is formed on the bonding pad exposed by the first opening. A photoresist having a second opening and a photoresist block disposed in the second opening is formed on the first metal layer. The first metal layer corresponding to the second opening has a first surface, and the first metal layer corresponding to the photoresist block has a second surface. A second metal layer is formed on the first surface, and the photoresist block is removed to expose the second surface. A UBM layer is formed on the second metal layer and the second surface of the first metal layer. Finally, a conductive bump is formed on the UBM layer.
摘要翻译：公开了一种芯片制造工艺。提供具有钝化层和至少一个焊盘的晶片。接合焊盘的表面暴露于钝化层的第一开口。在由第一开口暴露的接合焊盘上形成第一金属层。在第一金属层上形成具有第二开口和设置在第二开口中的光致抗蚀剂块的光致抗蚀剂。对应于第二开口的第一金属层具有第一表面，并且对应于光刻胶块的第一金属层具有第二表面。在第一表面上形成第二金属层，去除光致抗蚀剂块以露出第二表面。 UBM层形成在第二金属层和第一金属层的第二表面上。最后，在UBM层上形成导电凸块。

7. 发明授权

US08368216B2 Semiconductor package 有权
标题翻译：半导体封装
公开(公告)号：US08368216B2
公开(公告)日：2013-02-05
申请号：US12872644
申请日：2010-08-31
申请人： Yi-Shao Lai , Tsung-Yueh Tsai , Ming-Kun Chen , Hsiao-Chuan Chang , Ming-Hsiang Cheng
发明人： Yi-Shao Lai , Tsung-Yueh Tsai , Ming-Kun Chen , Hsiao-Chuan Chang , Ming-Hsiang Cheng
IPC分类号： H01L23/538 , H01L21/60 , H01L23/488
CPC分类号： H01L21/6835 , H01L21/563 , H01L21/568 , H01L23/3114 , H01L24/27 , H01L25/0652 , H01L25/50 , H01L2224/1184 , H01L2224/131 , H01L2224/1329 , H01L2224/16145 , H01L2224/2784 , H01L2224/73104 , H01L2224/73204 , H01L2224/81005 , H01L2224/81801 , H01L2224/8185 , H01L2224/831 , H01L2225/06513 , H01L2924/15311 , H01L2924/15321 , H01L2924/014
摘要： The present invention relates to a semiconductor package having at least one first layer chip, a plurality of first metal bumps, at least one second layer chip and a package body. The first layer chip includes a first active surface upon which the first metal bumps are disposed and a plurality of first signal coupling pads disposed adjacent to the first active surface. The second layer chip is electrically connected to the first layer chip, and includes a second active surface that faces the first active surface and a plurality of second signal coupling pads. The second signal coupling pads are capacitively coupled to the first signal coupling pads so as to provide proximity communication between the first layer chip and the second layer chip. The package body encapsulates the first layer chip, the first metal bumps, and the second layer chip, and the first metal bumps are partially exposed.
摘要翻译：本发明涉及具有至少一个第一层芯片，多个第一金属凸块，至少一个第二层芯片和封装体的半导体封装。第一层芯片包括设置有第一金属凸块的第一有源表面和与第一有源表面相邻设置的多个第一信号耦合焊盘。第二层芯片电连接到第一层芯片，并且包括面向第一有源表面的第二有源表面和多个第二信号耦合焊盘。第二信号耦合焊盘电容耦合到第一信号耦合焊盘，以便提供第一层芯片和第二层芯片之间的接近通信。封装体封装第一层芯片，第一金属凸块和第二层芯片，并且第一金属凸块部分地露出。

8. 发明申请

US20110278739A1 Semiconductor Package 审中-公开
标题翻译：半导体封装
公开(公告)号：US20110278739A1
公开(公告)日：2011-11-17
申请号：US12777442
申请日：2010-05-11
申请人： Yi-Shao Lai , Tsung-Yueh Tsai , Ming-Kun Chen , Hsiao-Chuan Chang , Ming-Hsiang Cheng
发明人： Yi-Shao Lai , Tsung-Yueh Tsai , Ming-Kun Chen , Hsiao-Chuan Chang , Ming-Hsiang Cheng
IPC分类号： H01L23/52
CPC分类号： H01L23/49827 , H01L23/147 , H01L23/48 , H01L23/481 , H01L24/48 , H01L25/0657 , H01L2224/05571 , H01L2224/05573 , H01L2224/16146 , H01L2224/16225 , H01L2224/16227 , H01L2224/48227 , H01L2225/0651 , H01L2225/06513 , H01L2225/06531 , H01L2225/06541 , H01L2225/06548 , H01L2225/06568 , H01L2225/06572 , H01L2924/00014 , H01L2924/10253 , H01L2924/1815 , H01L2924/19104 , H01L2924/19105 , H01L2924/00 , H01L2224/05599 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： The present invention relates to a semiconductor package. The semiconductor package includes a substrate, a first chip and an interposer. The first chip is mechanically and electrically connected to the substrate. Some signal pads of the interposer are capacitively coupled to some signal pads of the first chip, so as to provide proximity communication between the first chip and the interposer. Whereby, the capacitively coupled signal pads can be made in fine pitch, and therefore the size of the semiconductor package is reduced and the density of the signal pads is increased.
摘要翻译：本发明涉及半导体封装。半导体封装包括衬底，第一芯片和插入器。第一芯片机械地和电连接到基板。插入器的一些信号焊盘电容耦合到第一芯片的一些信号焊盘，以便在第一芯片和插入器之间提供接近通信。由此，电容耦合的信号焊盘可以以细间距制成，因此半导体封装的尺寸减小，信号焊盘的密度增加。

9. 发明授权

US07980757B2 Bonding strength measuring device 有权
标题翻译：接合强度测量装置
公开(公告)号：US07980757B2
公开(公告)日：2011-07-19
申请号：US12350643
申请日：2009-01-08
申请人： Yi-Shao Lai , Tsung-Yueh Tsai , Hsiao-Chuan Chang
发明人： Yi-Shao Lai , Tsung-Yueh Tsai , Hsiao-Chuan Chang
IPC分类号： G01K1/00 , G01N25/00
CPC分类号： G01N19/04
摘要： A bonding strength measuring device for measuring the bonding strength between a substrate and a molding compound disposed on the substrate is provided. The measuring device includes a heating platform, a heating slide plate, and a fixing bracket. The heating platform has a first heating area and a first replaceable fixture. The substrate is disposed on the first heating area, and the first replaceable fixture is used to fix the substrate and has an opening exposing the molding compound. The heating slide plate has a second heating area and a second replaceable fixture. The second heating area is used to heat the molding compound, and the second replaceable fixture has a cavity for accommodating the molding compound. The fixing bracket is used to fix the heating slide plate above the heating platform.
摘要翻译：提供了用于测量基板和设置在基板上的模塑料之间的接合强度的接合强度测量装置。测量装置包括加热平台，加热滑板和固定支架。加热平台具有第一加热区域和第一可更换夹具。基板设置在第一加热区域上，并且第一可更换夹具用于固定基板，并具有露出模塑料的开口。加热滑板具有第二加热区域和第二可更换夹具。第二加热区域用于加热模塑料，第二可更换夹具具有容纳模塑料的空腔。固定支架用于将加热滑板固定在加热平台上。

10. 发明申请

US20090175312A1 BONDING STRENGTH MEASURING DEVICE 有权
标题翻译：粘结强度测量装置
公开(公告)号：US20090175312A1
公开(公告)日：2009-07-09
申请号：US12350643
申请日：2009-01-08
申请人： Yi-Shao Lai , Tsung-Yueh Tsai , Hsiao-Chuan Chang
发明人： Yi-Shao Lai , Tsung-Yueh Tsai , Hsiao-Chuan Chang
IPC分类号： G01N3/00
CPC分类号： G01N19/04
摘要： A bonding strength measuring device for measuring the bonding strength between a substrate and a molding compound disposed on the substrate is provided. The measuring device includes a heating platform, a heating slide plate, and a fixing bracket. The heating platform has a first heating area and a first replaceable fixture. The substrate is disposed on the first heating area, and the first replaceable fixture is used to fix the substrate and has an opening exposing the molding compound. The heating slide plate has a second heating area and a second replaceable fixture. The second heating area is used to heat the molding compound, and the second replaceable fixture has a cavity for accommodating the molding compound. The fixing bracket is used to fix the heating slide plate above the heating platform.
摘要翻译：提供了用于测量基板和设置在基板上的模塑料之间的接合强度的接合强度测量装置。测量装置包括加热平台，加热滑板和固定支架。加热平台具有第一加热区域和第一可更换夹具。基板设置在第一加热区域上，并且第一可更换夹具用于固定基板，并具有露出模塑料的开口。加热滑板具有第二加热区域和第二可更换夹具。第二加热区域用于加热模塑料，第二可更换夹具具有用于容纳模塑料的空腔。固定支架用于将加热滑板固定在加热平台上。

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