专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20090051034A1 Semiconductor device and method for the same 审中-公开
标题翻译：半导体装置及其方法相同
公开(公告)号：US20090051034A1
公开(公告)日：2009-02-26
申请号：US11892103
申请日：2007-08-20
申请人： Chih-Yang Pai , Yuan-Hung Liu , Michael Kuang , Kuo-Ching Huang
发明人： Chih-Yang Pai , Yuan-Hung Liu , Michael Kuang , Kuo-Ching Huang
IPC分类号： H01L23/52 , H01L21/44
CPC分类号： H01L27/10888 , H01L21/76844
摘要： A method for forming a semiconductor device is provided. The method includes the following steps. A substrate having a first contact is provided. A layered structure is formed on the substrate. A recess is formed into the layered structure to expose at least a portion of the first contact. A glue layer is formed on the layered structure and the at least a portion of the first contact. The glue layer is removed from the at least a portion of the first contact. A second contact is formed contacting the first contact and the glue layer.
摘要翻译：提供一种形成半导体器件的方法。该方法包括以下步骤。提供具有第一触点的基板。在基板上形成层状结构。形成层状结构中的凹部以暴露第一接触件的至少一部分。在层状结构和第一接触的至少一部分上形成胶层。胶层从第一接触件的至少一部分去除。形成接触第一接触和胶层的第二接触。

2. 发明授权

US09082705B2 Method of forming an embedded memory device 有权
标题翻译：形成嵌入式存储器件的方法
公开(公告)号：US09082705B2
公开(公告)日：2015-07-14
申请号：US13566710
申请日：2012-08-03
申请人： Yu-Wei Ting , Kuo-Ching Huang , Chih-Yang Pai
发明人： Yu-Wei Ting , Kuo-Ching Huang , Chih-Yang Pai
IPC分类号： H01L21/336 , H01L21/4763 , H01L21/31 , H01L21/28 , H01L29/423 , H01L29/66 , H01L29/792
CPC分类号： H01L27/11521 , H01L21/28282 , H01L29/42324 , H01L29/42344 , H01L29/42356 , H01L29/66833 , H01L29/792
摘要： The present disclosure describes a method of forming a memory device. The method includes receiving a wafer substrate, forming a poly stack pattern on the wafer substrate, performing an ion implantation process to form a source and a drain in the wafer substrate, forming a memory gate and a control gate in the defined poly stack pattern, and forming a control gate in the control poly stack pattern. Forming the memory gate further includes performing a memory gate recess to bury the memory gate in an oxide layer.
摘要翻译：本公开描述了形成存储器件的方法。该方法包括接收晶片衬底，在晶片衬底上形成多晶堆叠图案，执行离子注入工艺以在晶片衬底中形成源极和漏极，在限定的多晶堆叠图案中形成存储栅极和控制栅极，以及在所述控制多晶堆叠图案中形成控制栅极。形成存储器栅极还包括执行存储器栅极凹槽以将存储栅极埋入氧化物层中。

3. 发明申请

US20140035020A1 Method of Forming an Embedded Memory Device 有权
标题翻译：形成嵌入式存储器件的方法
公开(公告)号：US20140035020A1
公开(公告)日：2014-02-06
申请号：US13566710
申请日：2012-08-03
申请人： Yu-Wei Ting , Kuo-Ching Huang , Chih-Yang Pai
发明人： Yu-Wei Ting , Kuo-Ching Huang , Chih-Yang Pai
IPC分类号： H01L29/788 , H01L21/336
CPC分类号： H01L27/11521 , H01L21/28282 , H01L29/42324 , H01L29/42344 , H01L29/42356 , H01L29/66833 , H01L29/792
摘要： The present disclosure describes a method of forming a memory device. The method includes receiving a wafer substrate, forming a poly stack pattern on the wafer substrate, performing an ion implantation process to form a source and a drain in the wafer substrate, forming a memory gate and a control gate in the defined poly stack pattern, and forming a control gate in the control poly stack pattern. Forming the memory gate further includes performing a memory gate recess to bury the memory gate in an oxide layer.
摘要翻译：本公开描述了形成存储器件的方法。该方法包括接收晶片衬底，在晶片衬底上形成多晶堆叠图案，执行离子注入工艺以在晶片衬底中形成源极和漏极，在限定的多晶堆叠图案中形成存储栅极和控制栅极，以及在所述控制多晶堆叠图案中形成控制栅极。形成存储器栅极还包括执行存储器栅极凹槽以将存储栅极埋入氧化物层中。

4. 发明申请

US20080318454A1 System and Method for Coupling an Integrated Circuit to a Circuit Board 有权
标题翻译：将集成电路耦合到电路板的系统和方法
公开(公告)号：US20080318454A1
公开(公告)日：2008-12-25
申请号：US11766204
申请日：2007-06-21
申请人： Chen-Fa Wu , Chih-Nan Lin , Kuo-Ching Huang , Chin-An Huang
发明人： Chen-Fa Wu , Chih-Nan Lin , Kuo-Ching Huang , Chin-An Huang
IPC分类号： H01R12/16
CPC分类号： H05K1/0271 , H05K2201/044 , H05K2201/09063 , H05K2201/10409 , H05K2201/10734
摘要： An information handling system circuit board has an opening formed through it proximate a coupling point of an integrated circuit to the circuit board. The opening manages stress at the coupling point of the integrated circuit to the circuit board to reduce the risk of damage to the coupling point during deformation of the circuit board, such as when the circuit board is coupled to a chassis or when a component is pressed into the circuit board. In one embodiment, rectangular openings are formed at diagonally opposed corners of a BSA integrated circuit. In alternative embodiments, openings of varying shape, such as slots or curved slots, are formed at selected corners of the integrated circuit.
摘要翻译：信息处理系统电路板具有通过其形成的开口，其靠近集成电路到电路板的耦合点。开口处理集成电路到电路板的耦合点处的应力，以减少在电路板变形期间对耦合点的损坏的风险，例如当电路板耦合到底盘或当部件被按压时进入电路板。在一个实施例中，在BSA集成电路的对角相对的角上形成矩形开口。在替代实施例中，在集成电路的选定角处形成变化形状的开口，例如槽或弯曲槽。

5. 发明申请

US20060061837A1 CLAMP FOR FIXING A PHOTOGRAPHIC SLIDE OR NEGATIVE 审中-公开
标题翻译：用于固定摄影幻灯片或负片的夹具
公开(公告)号：US20060061837A1
公开(公告)日：2006-03-23
申请号：US10904740
申请日：2004-11-24
申请人： Kuo-Ching Huang , Yu-Cheng Chang
发明人： Kuo-Ching Huang , Yu-Cheng Chang
IPC分类号： H04N1/23
CPC分类号： H04N1/1013 , H04N2201/0406 , H04N2201/0408 , H04N2201/0422
摘要： A clamp for fixing a photographic slide and/or a photographic negative includes a carrier and a cover for fixing the slide or negative onto the carrier. The carrier includes a first guide for holding the negative, and a second guide extended from the first guide for holding the photographic slide.
摘要翻译：用于固定照相底片和/或照相底片的夹具包括用于将滑块或阴极固定到载体上的载体和盖。载体包括用于保持负片的第一引导件和从第一引导件延伸以保持照相载玻片的第二引导件。

6. 发明授权

US07619166B2 Bus structure 有权
标题翻译：总线结构
公开(公告)号：US07619166B2
公开(公告)日：2009-11-17
申请号：US11136558
申请日：2005-05-25
申请人： Kuo-Ching Huang , Yu-Cheng Chang
发明人： Kuo-Ching Huang , Yu-Cheng Chang
IPC分类号： H01B7/08
CPC分类号： H05K1/147 , H04N1/00519 , H04N1/1017 , H04N1/193 , H04N2201/0081 , H05K1/144 , H05K2201/09109
摘要： A bus structure may include two or more soft buses and one or more soft separation layers. The two or more soft buses may be stacked side by side with respect to each other. The one or more soft separation layers may be sandwiched between two adjacent soft buses of the two or more soft buses.
摘要翻译：总线结构可以包括两个或更多个软总线和一个或多个软分离层。两个以上的软总线可以相对于彼此并排堆叠。一个或多个软分离层可以夹在两个或多个软总线的两个相邻的软总线之间。

7. 发明申请

US20070129189A1 Belt tension adjustment mechanism 审中-公开
标题翻译：皮带张力调节机制
公开(公告)号：US20070129189A1
公开(公告)日：2007-06-07
申请号：US11332340
申请日：2006-01-17
申请人： Kuo-Ching Huang , Yu-Cheng Chang
发明人： Kuo-Ching Huang , Yu-Cheng Chang
IPC分类号： F16H7/18 , F16H7/08
CPC分类号： F16H7/08 , F16H2007/0806 , F16H2007/0812
摘要： A belt tension adjustment mechanism for use in an optical module of a scanning apparatus includes a sliding member, a fixture member, a supporting member and a resilient member. The sliding member is arranged on a surface of the optical module and movable on the surface of the optical module. The fixture member is used to fix the belt. The supporting member supports the belt. By means of the resilient member, a tension is applied onto the belt.
摘要翻译：用于扫描装置的光学模块中的皮带张力调节机构包括滑动构件，固定构件，支撑构件和弹性构件。滑动构件布置在光学模块的表面上并且可在光学模块的表面上移动。固定件用于固定皮带。支撑构件支撑带。通过弹性构件，张力被施加到带上。

8. 发明申请

US20060164531A1 Structure for CMOS image sensor 有权
标题翻译： CMOS图像传感器的结构
公开(公告)号：US20060164531A1
公开(公告)日：2006-07-27
申请号：US11044922
申请日：2005-01-27
申请人： Dun-Nian Yaung , Kuo-Ching Huang , Ho-Ching Chien , Shou-Gwo Wuu
发明人： Dun-Nian Yaung , Kuo-Ching Huang , Ho-Ching Chien , Shou-Gwo Wuu
IPC分类号： H04N5/335
CPC分类号： H04N5/361 , H01L27/14603 , H01L27/14609 , H01L27/14643 , H01L27/14689 , H04N5/3559 , H04N5/374 , H04N5/37452
摘要： A CMOS image sensor having increased capacitance that allows a photo-diode to generate a larger current is provided. The increased capacitance reduces noise and the dark signal. The image sensor utilizes a transistor having nitride spacers formed on a buffer oxide layer. Additional capacitance may be provided by various capacitor structures, such as a stacked capacitor, a planar capacitor, a trench capacitor, a MOS capacitor, a MIM/PIP capacitor, or the like. Embodiments of the present invention may be utilized in a 4-transistor pixel or a 3-transistor pixel configuration.
摘要翻译：提供了具有允许光电二极管产生较大电流的增加的电容的CMOS图像传感器。增加的电容可以降低噪声和暗信号。图像传感器利用形成在缓冲氧化物层上的具有氮化物间隔物的晶体管。附加电容可以由诸如叠层电容器，平面电容器，沟槽电容器，MOS电容器，MIM / PIP电容器等的各种电容器结构来提供。本发明的实施例可以用于4-晶体管像素或3-晶体管像素配置。

9. 发明授权

US06880675B2 Multifunctional adjustable ladder assembly 失效
标题翻译：多功能可调梯组件
公开(公告)号：US06880675B2
公开(公告)日：2005-04-19
申请号：US10423607
申请日：2003-04-25
申请人： Kuo-Ching Huang
发明人： Kuo-Ching Huang
IPC分类号： E06C1/18 , E06C1/22 , E06C7/08 , E06C1/00
CPC分类号： E06C7/083 , E06C1/18 , E06C1/22
摘要： A ladder assembly includes two symmetric support stands pivotally connected with each other. Each of the two support stands includes a main frame, an upper frame, a lower frame, a top bar, a retraction control unit, and four fixing devices. Thus, height of the ladder assembly can be adjusted easily and conveniently, thereby facilitating the user operating the ladder assembly. In addition, the upper frame and the lower frame can be folded on the main frame, so as to reduce the volume the ladder assembly efficiently, thereby greatly facilitating storage and transportation of the ladder assembly.
摘要翻译：梯子组件包括彼此枢转连接的两个对称支撑架。两个支撑台中的每一个包括主框架，上框架，下框架，顶杆，缩回控制单元和四个固定装置。因此，可以容易且方便地调整梯子组件的高度，从而便于使用者操作梯子组件。此外，上框架和下框架可以折叠在主框架上，以便有效地减少梯子组件的体积，从而极大地方便了梯子组件的存储和运输。

10. 发明授权

US06661043B1 One-transistor RAM approach for high density memory application 有权
标题翻译：用于高密度存储器应用的单晶体管RAM方法
公开(公告)号：US06661043B1
公开(公告)日：2003-12-09
申请号：US10400401
申请日：2003-03-27
申请人： Kuo-Ching Huang , Wen-Cheng Chen , Wen-Chuan Chiang , Kuo-Chuang Tseng
发明人： Kuo-Ching Huang , Wen-Cheng Chen , Wen-Chuan Chiang , Kuo-Chuang Tseng
IPC分类号： H01L218242
CPC分类号： H01L27/1085 , H01L27/1087
摘要： A new method is provided for the creation of a 1T RAM cell. Standard processing is applied to create STI trenches in the surface of a substrate, N2 implantations are performed into the sidewalls of the STI trenches. A layer of lining oxide is created, the implanted N2 interacts with the lining oxide to form SiON over exposed surfaces of the STI trenches. STI oxide is deposited and polished, filling the STI trenches there-with. Crown patterning is performed to define capacitor areas, the crown patterning stops on a layer of etch stop material and the created SION and partially removes STI oxide from the STI trenches. Layers of etch stop material, exposed SiON and pad oxide are removed, exposing the surface of the silicon substrate, the etched layers of STI oxide are not affected by this removal. A layer of SAC oxide is grown, n-well and p-well implantations are performed into the surface of the substrate. The layer of SAC oxide is removed, gate oxide is grown, polysilicon is deposited and patterned and etched, forming polysilicon gate material and polysilicon top plate of the capacitor. Standard processing is further applied to complete the 1T-RAM cell by providing gate spacers and impurity implantations for the gate electrode, by saliciding contact surfaces and by providing contacts to the points of contact of the cell.
摘要翻译：提供了一种用于创建1T RAM单元的新方法。施加标准处理以在衬底的表面中产生STI沟槽，在STI沟槽的侧壁中进行N2注入。产生衬里氧化层，注入的N 2与衬里氧化物相互作用以在STI沟槽的暴露表面上形成SiON。沉积和抛光STI氧化物，在那里填充STI沟槽。进行冠图案化以限定电容器区域，冠图案停止在蚀刻停止材料层上，并且所产生的SION并且部分地从STI沟槽去除STI氧化物。蚀刻停止材料层，暴露的SiON和衬垫氧化物层被去除，暴露硅衬底的表面，STI氧化物的蚀刻层不受该去除的影响。生长一层SAC氧化物，n阱和p阱注入进行到衬底的表面。去除SAC氧化物层，生长栅极氧化物，沉积多晶硅并进行图案化和蚀刻，形成电容器的多晶硅栅极材料和多晶硅顶板。进一步应用标准处理，通过为栅电极提供栅极间隔物和杂质注入，通过对接触表面进行喷淋并且通过提供与电池的接触点的接触来完成1T-RAM单元。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式