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1. 发明授权

US5366079A Integrated circuit wafer and retainer element combination 失效
标题翻译：集成电路晶片和保持器元件组合
公开(公告)号：US5366079A
公开(公告)日：1994-11-22
申请号：US108249
申请日：1993-08-19
申请人： Chih-Ching Lin , Jiin C. Tai , Jane-Hong Huang , Ying-Kuang Peng
发明人： Chih-Ching Lin , Jiin C. Tai , Jane-Hong Huang , Ying-Kuang Peng
IPC分类号： H01L21/673 , B65D73/02 , B65D85/02 , B65D85/42
CPC分类号： H01L21/67369 , Y10S206/821
摘要： The container has an enclosure member and a body member which together enclose a volume to accept wafers for storage, for handling, or for transportation. The body member has a base, and a plurality of spaced upright arcuate members supported on the base that are adapted to encircle wafers stacked on the base. An enclosure member has a circular top wall and a cylindrically shaped wall that is adapted to encompass and enclose the arcuate members. The retainer element has a flat central portion, and a plurality of flexible outwardly extending flaps depending from the central portion. The retainer element fits within the arcuate members of the body member with the end portions of the flaps positioned in the slots between the arcuate members.
摘要翻译：容器具有封闭构件和主体构件，其一起封闭体积以接收用于存储，处理或运输的晶片。主体构件具有底座，以及支撑在基座上的多个间隔开的直立弓形构件，其适于环绕堆叠在基座上的晶片。外壳构件具有圆形顶壁和圆柱形壁，其适于包围和包围弓形构件。保持器元件具有平坦的中心部分和从中心部分悬垂的多个柔性向外延伸的翼片。保持器元件装配在主体构件的弓形构件内，翼片的端部位于弓形构件之间的槽中。

2. 发明授权

US08640074B2 Digital circuit block having reducing supply voltage drop and method for constructing the same 有权
标题翻译：具有降低电源电压降的数字电路块及其构造方法
公开(公告)号：US08640074B2
公开(公告)日：2014-01-28
申请号：US13298315
申请日：2011-11-17
申请人： Shen-Yu Huang , Chih-Ching Lin
发明人： Shen-Yu Huang , Chih-Ching Lin
IPC分类号： G06F17/50 , G01R27/16 , G01R31/20
CPC分类号： H01L27/0207 , H01L23/5223 , H01L23/5286 , H01L28/20 , H01L2924/0002 , H03K19/00346 , H01L2924/00
摘要： A digital circuit block includes first to fourth conducting segments, a digital logic, first and second conducting layers, and a dielectric layer. The first and second conducting segments are coupled to first and second supply voltages, respectively. The digital logic and dielectric layer are between the first and second conducting segments. The third conducting segment includes a first end electrically connected to the first conducting segment, a second end not electrically connected to the second conducting segment, and a first portion located at the first conducting layer. The fourth conducting segment includes a first end electrically connected to the second conducting segment, a second end not electrically connected to the first conducting segment, and a second portion located at the second conducting layer. The first and second portions and dielectric layer are formed a first capacitive element to reduce the supply voltage drop between the first and second supply voltages.
摘要翻译：数字电路块包括第一至第四导电段，数字逻辑，第一和第二导电层以及电介质层。第一和第二导电段分别耦合到第一和第二电源电压。数字逻辑和电介质层位于第一和第二导电段之间。第三导电段包括电连接到第一导电段的第一端，不电连接到第二导电段的第二端和位于第一导电层的第一部分。第四导电段包括电连接到第二导电段的第一端，不电连接到第一导电段的第二端和位于第二导电层的第二部分。第一和第二部分和电介质层形成第一电容元件以减小第一和第二电源电压之间的电源电压降。

3. 发明申请

US20070099125A1 Fabrication Method for a Damascene Bit Line Contact Plug 有权
标题翻译：大马士革钻头接头塞的制造方法
公开(公告)号：US20070099125A1
公开(公告)日：2007-05-03
申请号：US11564238
申请日：2006-11-28
申请人： Yi-Nan Chen , Jeng-Ping Lin , Chih-Ching Lin , Hui-Min Mao
发明人： Yi-Nan Chen , Jeng-Ping Lin , Chih-Ching Lin , Hui-Min Mao
IPC分类号： G03C5/00
CPC分类号： H01L21/76897 , H01L21/76885 , H01L27/105 , H01L27/1052 , H01L27/10888
摘要： A fabrication method for a damascene bit line contact plug. A semiconductor substrate has a first gate conductive structure, a second gate conductive structure and a source/drain region formed therebetween. A first conductive layer is formed in a space between the first gate conductive structure and the second gate conductive structure to be electrically connected to the source/drain region. An inter-layer dielectric with a planarized surface is formed to cover the first conductive layer, the first gate conductive structure, and the second gate conductive structure. A bit line contact hole is formed in the inter-layer dielectric to expose the top of the first conductive layer. A second conductive layer is formed in the bit line contact hole, in which the combination of the second conductive layer and the first conductive layer serves as a damascene bit line contact plug.
摘要翻译：镶嵌位线接触插头的制造方法。半导体衬底具有形成在其间的第一栅极导电结构，第二栅极导电结构和源极/漏极区。第一导电层形成在第一栅极导电结构和第二栅极导电结构之间的空间中，以电连接到源极/漏极区。形成具有平坦化表面的层间电介质以覆盖第一导电层，第一栅极导电结构和第二栅极导电结构。在层间电介质中形成位线接触孔，露出第一导电层的顶部。第二导电层形成在位线接触孔中，其中第二导电层和第一导电层的组合用作镶嵌位线接触插塞。

4. 发明授权

US08592320B2 Method for forming fin-shaped semiconductor structure 有权
标题翻译：形成鳍状半导体结构的方法
公开(公告)号：US08592320B2
公开(公告)日：2013-11-26
申请号：US13210172
申请日：2011-08-15
申请人： Chih-Ching Lin , Yi-Nan Chen , Hsien-Wen Liu
发明人： Chih-Ching Lin , Yi-Nan Chen , Hsien-Wen Liu
IPC分类号： H01L21/302
CPC分类号： H01L29/7854 , H01L29/7853
摘要： A method for fabricating a fin-shaped semiconductor structure is provided, including: providing a semiconductor substrate with a semiconductor island and a dielectric layer formed thereover; forming a mask layer over the semiconductor island and the dielectric layer; forming an opening in the mask layer, exposing a top surface of the semiconductor island and portions of the dielectric layer adjacent to the semiconductor island; performing an etching process, simultaneously etching portions of the mask layer, and portions of the semiconductor island and the dielectric layer exposed by the opening; and removing the mask layer and the dielectric layer, leaving an etched semiconductor island with curved top surfaces and various thicknesses over the semiconductor substrate.
摘要翻译：提供了一种制造鳍状半导体结构的方法，包括：提供半导体衬底和形成在其上的介电层的半导体衬底; 在所述半导体岛和所述电介质层上形成掩模层; 在所述掩模层中形成开口，使所述半导体岛的上表面和与所述半导体岛相邻的所述电介质层的部分露出; 进行蚀刻处理，同时蚀刻掩模层的一部分，以及由开口暴露的半导体岛和电介质层的部分; 并且去除掩模层和电介质层，在半导体衬底上留下具有弯曲顶表面和各种厚度的蚀刻半导体岛。

5. 发明申请

US20100181847A1 METHOD FOR REDUCING SUPPLY VOLTAGE DROP IN DIGITAL CIRCUIT BLOCK AND RELATED LAYOUT ARCHITECTURE 审中-公开
标题翻译：降低数字电路块供电电压的方法及相关布线架构
公开(公告)号：US20100181847A1
公开(公告)日：2010-07-22
申请号：US12358215
申请日：2009-01-22
申请人： Shen-Yu Huang , Chih-Ching Lin
发明人： Shen-Yu Huang , Chih-Ching Lin
IPC分类号： H05K7/06
CPC分类号： H01L27/0207 , H01L23/5223 , H01L23/5286 , H01L28/20 , H01L2924/0002 , H03K19/00346 , H01L2924/00
摘要： A method for reducing a supply voltage drop in a digital circuit block, where the digital circuit block includes a first conducting segment coupled to a first supply voltage, a second conducting segment coupled to a second supply voltage, and a digital logic coupled between the first conducting segment and the second conducting segment, the method including: constructing a third conducting segment connected to the first conducting segment and not electrically connected to the second conducting segment, wherein the third conducting segment is configured to have a first portion located at a first conducting layer; and constructing a fourth conducting segment electrically connected to the second conducting segment and not electrically connected to the first conducting segment, wherein the fourth conducting segment is configured to have a second portion located at a second conducting layer, and whereby a capacitive element is formed between the first portion and the second portion.
摘要翻译：一种用于减少数字电路块中的电源电压降的方法，其中所述数字电路块包括耦合到第一电源电压的第一导电段，耦合到第二电源电压的第二导电段和耦合在所述第一电源电压之间的数字逻辑导电段和第二导电段，所述方法包括：构造连接到所述第一导电段并且未电连接到所述第二导电段的第三导电段，其中所述第三导电段被配置为具有位于第一导电段层; 以及构造电连接到所述第二导电段并且不电连接到所述第一导电段的第四导电段，其中所述第四导电段被配置为具有位于第二导电层的第二部分，第一部分和第二部分。

6. 发明申请

US20080254589A1 METHOD FOR MANUFACTURING COLLARS OF DEEP TRENCH CAPACITORS 审中-公开
标题翻译：制造深层电容电容器的方法
公开(公告)号：US20080254589A1
公开(公告)日：2008-10-16
申请号：US11829067
申请日：2007-07-26
申请人： Jen-Jui Huang , Chih-Ching Lin
发明人： Jen-Jui Huang , Chih-Ching Lin
IPC分类号： H01L21/20
CPC分类号： H01L29/66181 , H01L27/1087
摘要： A method for manufacturing collars of deep trench capacitors includes providing a substrate with a deep trench in which there is a trench capacitor in the bottom; forming an inner wall layer completely covering the deep trench and the substrate; forming a hard mask layer on the surface of the inner wall layer; performing a selective implanting but not on the hard mask layer on the wall of the deep trench; performing a selective wet etching to remove the not implanted hard mask layer; and performing an anisotropic dry etching to substantially remove the inner wall layer on the bottom of the deep trench so as to partially expose the trench capacitor and to substantially retain the collars of the deep trench capacitors intact.
摘要翻译：一种用于制造深沟槽电容器的套环的方法包括：向衬底提供深沟槽，其中在底部存在沟槽电容器; 形成完全覆盖深沟槽和衬底的内壁层; 在内壁层的表面上形成硬掩模层; 执行选择性植入，但不在深沟槽的壁上的硬掩模层上进行; 执行选择性湿蚀刻以去除未注入的硬掩模层; 并进行各向异性干蚀刻以基本上去除深沟槽底部的内壁层，以便部分地暴露沟槽电容器并且基本上保持深沟槽电容器的套环完好无损。

7. 发明申请

US20080172105A1 Method for preventing and/or ameliorating inflammation 审中-公开
标题翻译：预防和/或改善炎症的方法
公开(公告)号：US20080172105A1
公开(公告)日：2008-07-17
申请号：US11896879
申请日：2007-09-06
申请人： Chih-Ching Lin , Chyi-Ran Lee
发明人： Chih-Ching Lin , Chyi-Ran Lee
IPC分类号： A61B18/18
CPC分类号： A61N5/0613 , A61N2005/066
摘要： A method for preventing and/or ameliorating inflammation. The method comprises irradiating a biological subject with an electromagnetic wave from an emitter, wherein the electromagnetic wave has a wavelength of about 1.5 to 100 μm μm, and the biological subject can be a peripheral vascular disease patient. Additionally, the method of the invention can improve the access blood flow and unassisted patency of arteriovenous fistula in hemodialysis patients.
摘要翻译：一种预防和/或改善炎症的方法。该方法包括用来自发射器的电磁波照射生物学对象，其中电磁波具有大约1.5至100个妈妈的波长，生物学对象可以是外周血管疾病患者。此外，本发明的方法可以改善血液透析患者的动静脉瘘的通路血流量和无辅助通畅。

8. 发明授权

US07067418B2 Interconnect structure and method for fabricating the same 有权
公开(公告)号：US07067418B2
公开(公告)日：2006-06-27
申请号：US10908824
申请日：2005-05-27
申请人： Tse-Yao Huang , Yi-Nan Chen , Chih-Ching Lin
发明人： Tse-Yao Huang , Yi-Nan Chen , Chih-Ching Lin
IPC分类号： H01L21/4763
CPC分类号： H01L21/7685 , H01L21/76802 , H01L21/76832 , H01L21/76837
摘要： A method for fabricating interconnects is provided. The method comprises forming a conducting line on a first dielectric layer; forming a first liner layer on the surfaces of the first dielectric layer and the conducting line; forming a second liner layer on the first liner layer; forming a second dielectric layer on the second liner layer, wherein the etching selectivity rate of the second dielectric layer is higher than the etching selectivity rate of the second liner; and patterning the second dielectric layer to form a contact window opening through the second liner layer and the first liner layer to expose the surface of the conducting line. Because the second dielectric layer having an etching rate higher than the etching rate of the second liner layer, the second liner layer can be used as an etch stop layer while patterning the second dielectric layer.

9. 发明授权

US08772928B2 Integrated circuit chip with reduced IR drop 有权
标题翻译：集成电路芯片具有降低的IR降
公开(公告)号：US08772928B2
公开(公告)日：2014-07-08
申请号：US13205648
申请日：2011-08-09
申请人： Chih-Ching Lin , Ya-Ting Chang , Chia-Lin Chuang
发明人： Chih-Ching Lin , Ya-Ting Chang , Chia-Lin Chuang
IPC分类号： H01L23/48
CPC分类号： H01L23/5286 , H01L23/5223 , H01L24/05
摘要： An integrated circuit chip includes a power/ground interconnection network in a topmost metal layer over a semiconductor substrate and at least a bump pad on/over the power/ground interconnection network. The power/ground mesh interconnection network includes a first power/ground line connected to the bump pad and extending along a first direction, and a connection portion connected to the bump pad and extending along a second direction.
摘要翻译：集成电路芯片包括位于半导体衬底上的最顶层金属层中的电源/接地互连网络，以及至少在电力/接地互连网络上/之上的凸块焊盘。电源/接地网状互连网络包括连接到凸块焊盘并沿着第一方向延伸的第一电源/接地线，以及连接到凸块焊盘并沿第二方向延伸的连接部分。

10. 发明授权

US07949988B2 Layout circuit having a combined tie cell 有权
标题翻译：布局电路具有组合的连接单元
公开(公告)号：US07949988B2
公开(公告)日：2011-05-24
申请号：US12060298
申请日：2008-04-01
申请人： Tung-Kai Tsai , Chih-Ching Lin
发明人： Tung-Kai Tsai , Chih-Ching Lin
IPC分类号： G06F17/50 , G06F15/04 , H03K19/013 , H03K19/00 , H03K19/094
CPC分类号： G06F17/5068 , G06F2217/72 , H01L27/0207 , H01L27/11807
摘要： A layout circuit is provided, comprising standard cells, a spare cell, combined tie cells and normal filler cells. The standard cells are disposed and routed on a layout area. The spare cell is added on the layout area and provided for replacing one of the standard cells while adding or changing functions later. The combined tie cells are added on the layout area. The normal filler cells are added on the rest of the layout area. The combined tie cell comprises a tie-high circuit, a tie-low circuit and a capacitance circuit. Some standard cells are disposed near at least one combined tie cell for avoiding routing congestion between the combined tie cells and the replaced standard cell. A circuit layout method is also provided.
摘要翻译：提供了一种布局电路，包括标准单元，备用单元，组合连接单元和普通填充单元。标准单元被布置并布置在布局区域上。在布局区域中添加备用单元，并在稍后添加或更改功能时提供替换其中一个标准单元。组合的领带单元被添加在布局区域上。正常填充单元被添加到布局区域的其余部分。组合式连接单元包括连接高电路，连接低电路和电容电路。一些标准单元设置在至少一个组合的连接单元附近，以避免组合连接单元与替换的标准单元之间的路由拥塞。还提供了电路布局方法。

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