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1. 发明授权

US09490342B2 Method for fabricating semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US09490342B2
公开(公告)日：2016-11-08
申请号：US13161591
申请日：2011-06-16
申请人： Chien-Ming Lai , Yi-Wen Chen , Zhi-Cheng Lee , Tong-Jyun Huang , Che-Hua Hsu , Kun-Hsien Lin , Tzung-Ying Lee , Chi-Mao Hsu , Hsin-Fu Huang , Chin-Fu Lin
发明人： Chien-Ming Lai , Yi-Wen Chen , Zhi-Cheng Lee , Tong-Jyun Huang , Che-Hua Hsu , Kun-Hsien Lin , Tzung-Ying Lee , Chi-Mao Hsu , Hsin-Fu Huang , Chin-Fu Lin
IPC分类号： H01L21/3205 , H01L29/66 , H01L21/8238 , H01L21/28 , H01L21/3213 , H01L29/423 , H01L29/49 , H01L29/51 , H01L29/78
CPC分类号： H01L29/6659 , H01L21/28088 , H01L21/32134 , H01L21/823842 , H01L29/42376 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66545 , H01L29/7833
摘要： A method for fabricating a semiconductor device includes the following steps. Firstly, a dummy gate structure having a dummy gate electrode layer is provided. Then, the dummy gate electrode layer is removed to form an opening in the dummy gate structure, thereby exposing an underlying layer beneath the dummy gate electrode layer. Then, an ammonium hydroxide treatment process is performed to treat the dummy gate structure. Afterwards, a metal material is filled into the opening.
摘要翻译：一种制造半导体器件的方法包括以下步骤。首先，提供具有伪栅极电极层的虚拟栅极结构。然后，去除虚拟栅极电极层，以在虚拟栅极结构中形成开口，从而暴露在伪栅极电极层下面的下面的层。然后，进行氢氧化铵处理处理以处理伪栅极结构。之后，将金属材料填充到开口中。

2. 发明授权

US09384962B2 Oxygen treatment of replacement work-function metals in CMOS transistor gates 有权
标题翻译： CMOS晶体管栅极中替代工作功能金属的氧化处理
公开(公告)号：US09384962B2
公开(公告)日：2016-07-05
申请号：US13082387
申请日：2011-04-07
申请人： Guang-Yaw Hwang , Chun-Hsien Lin , Hung-Ling Shih , Jiunn-Hsiung Liao , Zhi-Cheng Lee , Shao-Hua Hsu , Yi-Wen Chen , Cheng-Guo Chen , Jung-Tsung Tseng , Chien-Ting Lin , Tong-Jyun Huang , Jie-Ning Yang , Tsung-Lung Tsai , Po-Jui Liao , Chien-Ming Lai , Ying-Tsung Chen , Cheng-Yu Ma , Wen-Han Hung , Che-Hua Hsu
发明人： Guang-Yaw Hwang , Chun-Hsien Lin , Hung-Ling Shih , Jiunn-Hsiung Liao , Zhi-Cheng Lee , Shao-Hua Hsu , Yi-Wen Chen , Cheng-Guo Chen , Jung-Tsung Tseng , Chien-Ting Lin , Tong-Jyun Huang , Jie-Ning Yang , Tsung-Lung Tsai , Po-Jui Liao , Chien-Ming Lai , Ying-Tsung Chen , Cheng-Yu Ma , Wen-Han Hung , Che-Hua Hsu
IPC分类号： H01L21/28 , H01L21/02
CPC分类号： H01L29/517 , H01L21/28088 , H01L21/823842 , H01L21/823857 , H01L29/4966 , H01L29/513 , H01L29/66545 , H01L29/6656 , H01L29/6659 , H01L29/7833 , H01L29/7843 , H01L29/7845 , H01L29/7846
摘要： A method of manufacturing a metal gate is provided. The method includes providing a substrate. Then, a gate dielectric layer is formed on the substrate. A multi-layered stack structure having a work function metal layer is formed on the gate dielectric layer. An O2 ambience treatment is performed on at least one layer of the multi-layered stack structure. A conductive layer is formed on the multi-layered stack structure.
摘要翻译：提供一种制造金属栅极的方法。该方法包括提供基板。然后，在基板上形成栅极电介质层。在栅极电介质层上形成具有功函数金属层的多层堆叠结构。在多层堆叠结构的至少一层上进行O2气氛处理。在多层堆叠结构上形成导电层。

3. 发明申请

US20120256276A1 Metal Gate and Fabricating Method Thereof 有权
标题翻译：金属门及其制造方法
公开(公告)号：US20120256276A1
公开(公告)日：2012-10-11
申请号：US13082387
申请日：2011-04-07
申请人： Guang-Yaw Hwang , Chun-Hsien Lin , Hung-Ling Shih , Jiunn-Hsiung Liao , Zhi-Cheng Lee , Shao-Hua Hsu , Yi-Wen Chen , Cheng-Guo Chen , Jung-Tsung Tseng , Chien-Ting Lin , Tong-Jyun Huang , Jie-Ning Yang , Tsung-Lung Tsai , Po-Jui Liao , Chien-Ming Lai , Ying-Tsung Chen , Cheng-Yu Ma , Wen-Han Hung , Che-Hua Hsu
发明人： Guang-Yaw Hwang , Chun-Hsien Lin , Hung-Ling Shih , Jiunn-Hsiung Liao , Zhi-Cheng Lee , Shao-Hua Hsu , Yi-Wen Chen , Cheng-Guo Chen , Jung-Tsung Tseng , Chien-Ting Lin , Tong-Jyun Huang , Jie-Ning Yang , Tsung-Lung Tsai , Po-Jui Liao , Chien-Ming Lai , Ying-Tsung Chen , Cheng-Yu Ma , Wen-Han Hung , Che-Hua Hsu
IPC分类号： H01L29/78 , H01L21/3205
CPC分类号： H01L29/517 , H01L21/28088 , H01L21/823842 , H01L21/823857 , H01L29/4966 , H01L29/513 , H01L29/66545 , H01L29/6656 , H01L29/6659 , H01L29/7833 , H01L29/7843 , H01L29/7845 , H01L29/7846
摘要： A method of manufacturing a metal gate is provided. The method includes providing a substrate. Then, a gate dielectric layer is formed on the substrate. A multi-layered stack structure having a work function metal layer is formed on the gate dielectric layer. An O2 ambience treatment is performed on at least one layer of the multi-layered stack structure. A conductive layer is formed on the multi-layered stack structure.
摘要翻译：提供一种制造金属栅极的方法。该方法包括提供基板。然后，在基板上形成栅极电介质层。在栅极电介质层上形成具有功函数金属层的多层堆叠结构。在多层堆叠结构的至少一层上进行O2气氛处理。在多层堆叠结构上形成导电层。

4. 发明申请

US20130280900A1 MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE HAVING METAL GATE 有权
标题翻译：具有金属栅的半导体器件的制造方法
公开(公告)号：US20130280900A1
公开(公告)日：2013-10-24
申请号：US13454337
申请日：2012-04-24
申请人： Chien-Ming Lai , Rai-Min Huang , Tong-Jyun Huang , Che-Hua Hsu , Yi-Wen Chen
发明人： Chien-Ming Lai , Rai-Min Huang , Tong-Jyun Huang , Che-Hua Hsu , Yi-Wen Chen
IPC分类号： H01L21/283
CPC分类号： H01L21/823842 , H01L29/66545
摘要： A manufacturing method for a semiconductor device having a metal gate is provided. First and second gate trenches are respectively formed in first and second semiconductor devices. A work-function metal layer is formed in the first and second gate trenches. A shielding layer is formed on the substrate. A first removing step is performed, so that the remaining shielding layer is at bottom of the second gate trench and fills up the first gate trench. A second removing step is performed, so that the remaining shielding layer is at bottom of the first gate trench to expose the work-function metal layer at sidewall of the first gate trench and in the second gate trench. The work-function metal layer not covered by the remaining shielding layer is removed, so that the remaining work-function metal layer is only at bottom of the first gate trench. The remaining shielding layer is removed.
摘要翻译：提供一种具有金属栅极的半导体器件的制造方法。第一和第二栅极沟槽分别形成在第一和第二半导体器件中。工作功能金属层形成在第一和第二栅极沟槽中。在基板上形成屏蔽层。执行第一去除步骤，使得剩余的屏蔽层位于第二栅极沟槽的底部并填充第一栅极沟槽。执行第二去除步骤，使得剩余的屏蔽层位于第一栅极沟槽的底部，以在第一栅极沟槽的侧壁和第二栅极沟槽中露出功函数金属层。除去未被剩余屏蔽层覆盖的功函数金属层，使剩余的功函数金属层仅在第一栅极沟槽的底部。剩下的屏蔽层被去除。

5. 发明授权

US08951855B2 Manufacturing method for semiconductor device having metal gate 有权
标题翻译：具有金属栅极的半导体器件的制造方法
公开(公告)号：US08951855B2
公开(公告)日：2015-02-10
申请号：US13454337
申请日：2012-04-24
申请人： Chien-Ming Lai , Rai-Min Huang , Tong-Jyun Huang , Che-Hua Hsu , Yi-Wen Chen
发明人： Chien-Ming Lai , Rai-Min Huang , Tong-Jyun Huang , Che-Hua Hsu , Yi-Wen Chen
IPC分类号： H01L21/8238
CPC分类号： H01L21/823842 , H01L29/66545
摘要： A manufacturing method for a semiconductor device having a metal gate is provided. First and second gate trenches are respectively formed in first and second semiconductor devices. A work-function metal layer is formed in the first and second gate trenches. A shielding layer is formed on the substrate. A first removing step is performed, so that the remaining shielding layer is at bottom of the second gate trench and fills up the first gate trench. A second removing step is performed, so that the remaining shielding layer is at bottom of the first gate trench to expose the work-function metal layer at sidewall of the first gate trench and in the second gate trench. The work-function metal layer not covered by the remaining shielding layer is removed, so that the remaining work-function metal layer is only at bottom of the first gate trench. The remaining shielding layer is removed.
摘要翻译：提供一种具有金属栅极的半导体器件的制造方法。第一和第二栅极沟槽分别形成在第一和第二半导体器件中。工作功能金属层形成在第一和第二栅极沟槽中。在基板上形成屏蔽层。执行第一去除步骤，使得剩余的屏蔽层位于第二栅极沟槽的底部并填充第一栅极沟槽。执行第二去除步骤，使得剩余的屏蔽层位于第一栅极沟槽的底部，以在第一栅极沟槽的侧壁和第二栅极沟槽中露出功函数金属层。除去未被剩余屏蔽层覆盖的功函数金属层，使剩余的功函数金属层仅在第一栅极沟槽的底部。剩下的屏蔽层被去除。

6. 发明申请

US20100317182A1 METHOD FOR MAKING SEMICONDUCTOR ELEMENT STRUCTURE 有权
标题翻译：制造半导体元件结构的方法
公开(公告)号：US20100317182A1
公开(公告)日：2010-12-16
申请号：US12862799
申请日：2010-08-25
申请人： Tian-Fu Chiang , Li-Wei Cheng , Che-Hua Hsu , Chih-Hao Yu , Cheng-Hsien Chou , Chien-Ming Lai , Yi-Wen Chen , Chien-Ting Lin , Guang-Hwa Ma
发明人： Tian-Fu Chiang , Li-Wei Cheng , Che-Hua Hsu , Chih-Hao Yu , Cheng-Hsien Chou , Chien-Ming Lai , Yi-Wen Chen , Chien-Ting Lin , Guang-Hwa Ma
IPC分类号： H01L21/8234
CPC分类号： H01L29/517 , H01L21/823842 , H01L21/823871 , H01L27/11 , H01L27/1104 , H01L29/495 , H01L29/4966 , H01L29/66545
摘要： A method for forming a semiconductor element structure is provided. First, a substrate including a first MOS and a second MOS is provided. The gate electrode of the first MOS is connected to the gate electrode of the second MOS, wherein the first MOS includes a first high-K material and a first metal for use in a first gate, and a second MOS includes a second high-K material and a second metal for use in a second gate. Then the first gate and the second gate are partially removed to form a connecting recess. Afterwards, the connecting recess is filled with a conductive material to form a bridge channel for electrically connecting the first metal and the second metal.
摘要翻译：提供一种形成半导体元件结构的方法。首先，提供包括第一MOS和第二MOS的基板。第一MOS的栅电极连接到第二MOS的栅电极，其中第一MOS包括第一高K材料和用于第一栅极的第一金属，第二MOS包括第二高K 材料和用于第二栅极的第二金属。然后，第一栅极和第二栅极被部分地去除以形成连接凹部。之后，用导电材料填充连接凹部，以形成用于电连接第一金属和第二金属的桥接通道。

7. 发明申请

US20120064679A1 METAL GATE TRANSISTOR AND METHOD FOR FABRICATING THE SAME 有权
标题翻译：金属栅极晶体管及其制造方法
公开(公告)号：US20120064679A1
公开(公告)日：2012-03-15
申请号：US13304409
申请日：2011-11-25
申请人： Chih-Hao Yu , Li-Wei Cheng , Che-Hua Hsu , Cheng-Hsien Chou , Tian-Fu Chiang , Chien-Ming Lai , Yi-Wen Chen , Jung-Tsung Tseng , Chien-Ting Lin , Guang-Hwa Ma
发明人： Chih-Hao Yu , Li-Wei Cheng , Che-Hua Hsu , Cheng-Hsien Chou , Tian-Fu Chiang , Chien-Ming Lai , Yi-Wen Chen , Jung-Tsung Tseng , Chien-Ting Lin , Guang-Hwa Ma
IPC分类号： H01L21/8238
CPC分类号： H01L29/6656 , H01L21/823807 , H01L21/823814 , H01L21/823842 , H01L29/165 , H01L29/495 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/66545 , H01L29/66636 , H01L29/7848
摘要： A method for fabricating metal gate transistor is disclosed. First, a substrate having a first transistor region and a second transistor region is provided. Next, a stacked film is formed on the substrate, in which the stacked film includes at least one high-k dielectric layer and a first metal layer. The stacked film is patterned to form a plurality of gates in the first transistor region and the second transistor region, a dielectric layer is formed on the gates, and a portion of the dielectric layer is planarized until reaching the top of each gates. The first metal layer is removed from the gate of the second transistor region, and a second metal layer is formed over the surface of the dielectric layer and each gate for forming a plurality of metal gates in the first transistor region and the second transistor region.
摘要翻译：公开了一种用于制造金属栅极晶体管的方法。首先，提供具有第一晶体管区域和第二晶体管区域的衬底。接下来，在基板上形成层叠膜，其中层叠膜包括至少一个高k电介质层和第一金属层。图案化层叠的膜以在第一晶体管区域和第二晶体管区域中形成多个栅极，在栅极上形成电介质层，并且介电层的一部分被平坦化，直到到达每个栅极的顶部。第一金属层从第二晶体管区域的栅极去除，并且第二金属层形成在电介质层的表面上，每个栅极用于在第一晶体管区域和第二晶体管区域中形成多个金属栅极。

8. 发明授权

US07932146B2 Metal gate transistor and polysilicon resistor and method for fabricating the same 有权
标题翻译：金属栅极晶体管和多晶硅电阻及其制造方法
公开(公告)号：US07932146B2
公开(公告)日：2011-04-26
申请号：US12052728
申请日：2008-03-20
申请人： Yi-Wen Chen , Li-Wei Cheng , Che-Hua Hsu , Chih-Hao Yu , Cheng-Hsien Chou , Chien-Ming Lai , Tian-Fu Chiang , Chien-Ting Lin , Guang-Hwa Ma
发明人： Yi-Wen Chen , Li-Wei Cheng , Che-Hua Hsu , Chih-Hao Yu , Cheng-Hsien Chou , Chien-Ming Lai , Tian-Fu Chiang , Chien-Ting Lin , Guang-Hwa Ma
IPC分类号： H01L21/8234 , H01L29/76
CPC分类号： H01L21/823807 , H01L21/28079 , H01L21/823814 , H01L21/823842 , H01L27/0629 , H01L29/4958 , H01L29/66545 , H01L29/6659 , H01L29/7833
摘要： A method for fabricating metal gate transistors and a polysilicon resistor is disclosed. First, a substrate having a transistor region and a resistor region is provided. A polysilicon layer is then formed on the substrate to cover the transistor region and the resistor region of the substrate. Next, a portion of the polysilicon layer disposed in the resistor is removed, and the remaining polysilicon layer is patterned to create a step height between the surface of the polysilicon layer disposed in the transistor region and the surface of the polysilicon layer disposed in the resistor region.
摘要翻译：公开了一种用于制造金属栅极晶体管和多晶硅电阻器的方法。首先，提供具有晶体管区域和电阻器区域的基板。然后在衬底上形成多晶硅层以覆盖衬底的晶体管区域和电阻器区域。接下来，去除设置在电阻器中的多晶硅层的一部分，并且对剩余的多晶硅层进行图案化以在布置在晶体管区域中的多晶硅层的表面和设置在电阻器中的多晶硅层的表面之间产生台阶高度地区。

9. 发明申请

US20110018072A1 METAL GATE TRANSISTOR AND METHOD FOR FABRICATING THE SAME 审中-公开
标题翻译：金属栅极晶体管及其制造方法
公开(公告)号：US20110018072A1
公开(公告)日：2011-01-27
申请号：US12894130
申请日：2010-09-29
申请人： Chien-Ting Lin , Li-Wei Cheng , Jung-Tsung Tseng , Che-Hua Hsu , Chih-Hao Yu , Tian-Fu Chiang , Yi-Wen Chen , Chien-Ming Lai , Cheng-Hsien Chou
发明人： Chien-Ting Lin , Li-Wei Cheng , Jung-Tsung Tseng , Che-Hua Hsu , Chih-Hao Yu , Tian-Fu Chiang , Yi-Wen Chen , Chien-Ming Lai , Cheng-Hsien Chou
IPC分类号： H01L29/772
CPC分类号： H01L29/66545 , H01L21/823807 , H01L21/823814 , H01L21/823857 , H01L29/495 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/665 , H01L29/6656 , H01L29/66583 , H01L29/66636 , H01L29/7848 , Y10S438/926
摘要： A metal gate transistor is disclosed. The metal gate transistor preferably includes: a substrate, a metal gate disposed on the substrate, and a source/drain region disposed in the substrate with respect to two sides of the metal gate. The metal gate includes a U-shaped high-k dielectric layer, a U-shaped cap layer disposed over the surface of the U-shaped high-k dielectric layer, and a U-shaped metal layer disposed over the U-shaped cap layer.
摘要翻译：公开了一种金属栅极晶体管。金属栅极晶体管优选地包括：衬底，设置在衬底上的金属栅极和相对于金属栅极的两侧设置在衬底中的源极/漏极区域。金属栅极包括U形高k电介质层，设置在U形高k电介质层表面上的U形盖层和设置在U形盖层上的U形金属层。

10. 发明申请

US20100052074A1 METAL GATE TRANSISTOR AND METHOD FOR FABRICATING THE SAME 有权
标题翻译：金属栅极晶体管及其制造方法
公开(公告)号：US20100052074A1
公开(公告)日：2010-03-04
申请号：US12198128
申请日：2008-08-26
申请人： Chien-Ting Lin , Li-Wei Cheng , Jung-Tsung Tseng , Che-Hua Hsu , Chih-Hao Yu , Tian-Fu Chiang , Yi-Wen Chen , Chien-Ming Lai , Cheng-Hsien Chou
发明人： Chien-Ting Lin , Li-Wei Cheng , Jung-Tsung Tseng , Che-Hua Hsu , Chih-Hao Yu , Tian-Fu Chiang , Yi-Wen Chen , Chien-Ming Lai , Cheng-Hsien Chou
IPC分类号： H01L47/00 , H01L21/336
CPC分类号： H01L29/66545 , H01L21/823807 , H01L21/823814 , H01L21/823857 , H01L29/495 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/665 , H01L29/6656 , H01L29/66583 , H01L29/66636 , H01L29/7848 , Y10S438/926
摘要： A method for fabricating a transistor having metal gate is disclosed. First, a substrate is provided, in which the substrate includes a first transistor region and a second transistor region. A plurality of dummy gates is formed on the substrate, and a dielectric layer is deposited on the dummy gate. The dummy gates are removed to form a plurality of openings in the dielectric layer. A high-k dielectric layer is formed to cover the surface of the dielectric layer and the opening, and a cap layer is formed on the high-k dielectric layer thereafter. The cap layer disposed in the second transistor region is removed, and a metal layer is deposited on the cap layer of the first transistor region and the high-k dielectric layer of the second transistor region. A conductive layer is formed to fill the openings of the first transistor region and the second transistor region.
摘要翻译：公开了一种用于制造具有金属栅极的晶体管的方法。首先，提供衬底，其中衬底包括第一晶体管区域和第二晶体管区域。在基板上形成多个虚拟栅极，在虚拟栅极上淀积介质层。去除虚拟栅极以在电介质层中形成多个开口。形成高k电介质层以覆盖电介质层和开口的表面，此后在高k电介质层上形成覆盖层。去除设置在第二晶体管区域中的盖层，并且在第一晶体管区域的帽层和第二晶体管区域的高k电介质层上沉积金属层。形成导电层以填充第一晶体管区域和第二晶体管区域的开口。

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