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1. 发明申请

US20110109238A1 Digital dimming device and digital dimming method 有权
标题翻译：数字调光装置和数字调光方式
公开(公告)号：US20110109238A1
公开(公告)日：2011-05-12
申请号：US12925504
申请日：2010-10-22
申请人： Chien-Fu Tang , Isaac Chen , An-Tung Chen
发明人： Chien-Fu Tang , Isaac Chen , An-Tung Chen
IPC分类号： H05B37/02
CPC分类号： H05B33/0827 , H05B33/0818
摘要： The present invention discloses a digital dimming device and a digital dimming method, for controlling a plurality of light emitting device channels. The method comprises: generating a corresponding plurality of driving signals to control the plurality of light emitting device channels; receiving a PWM input signal having a duty ratio, and phase shifting the PWM input signal to generate multiple PWM output signals with about the same duty ratio as the PWM input signal, but with respectively shifted phases; and enabling or disabling corresponding driving signals by the multiple PWM output signals, respectively.
摘要翻译：本发明公开了一种用于控制多个发光装置通道的数字调光装置和数字调光方法。该方法包括：产生相应的多个驱动信号以控制多个发光装置通道; 接收具有占空比的PWM输入信号，并且相位移PWM输入信号以产生与PWM输入信号大致相同占空比的多个PWM输出信号，但分别转换相位; 以及通过多个PWM输出信号分别启用或禁用相应的驱动信号。

2. 发明授权

US08643292B2 Digital dimming device and digital dimming method 有权
标题翻译：数字调光装置和数字调光方式
公开(公告)号：US08643292B2
公开(公告)日：2014-02-04
申请号：US12925504
申请日：2010-10-22
申请人： Chien-Fu Tang , Isaac Chen , An-Tung Chen
发明人： Chien-Fu Tang , Isaac Chen , An-Tung Chen
IPC分类号： G05F1/00
CPC分类号： H05B33/0827 , H05B33/0818
摘要： The present invention discloses a digital dimming device and a digital dimming method, for controlling a plurality of light emitting device channels. The method comprises: generating a corresponding plurality of driving signals to control the plurality of light emitting device channels; receiving a PWM input signal having a duty ratio, and phase shifting the PWM input signal to generate multiple PWM output signals with about the same duty ratio as the PWM input signal, but with respectively shifted phases; and enabling or disabling corresponding driving signals by the multiple PWM output signals, respectively.
摘要翻译：本发明公开了一种用于控制多个发光装置通道的数字调光装置和数字调光方法。该方法包括：产生相应的多个驱动信号以控制多个发光装置通道; 接收具有占空比的PWM输入信号，并且相位移PWM输入信号以产生与PWM输入信号大致相同占空比的多个PWM输出信号，但分别转换相位; 以及通过多个PWM输出信号分别启用或禁用相应的驱动信号。

3. 发明授权

US09362834B2 Flyback power supply circuit with programmable function and control method thereof 有权
标题翻译：具有可编程功能的反激式电源电路及其控制方法
公开(公告)号：US09362834B2
公开(公告)日：2016-06-07
申请号：US14739894
申请日：2015-06-15
申请人： Chien-Fu Tang , Isaac Y. Chen , Kuang-Fu Chang , Hsin-Yi Wu , An-Tung Chen
发明人： Chien-Fu Tang , Isaac Y. Chen , Kuang-Fu Chang , Hsin-Yi Wu , An-Tung Chen
IPC分类号： H02M1/32 , H02M3/335 , H02H7/122 , H02M1/00
CPC分类号： H02M3/33523 , H02M1/32 , H02M3/33515 , H02M2001/0025
摘要： The present invention discloses a flyback power supply circuit with a programmable function and a control method thereof. The flyback power supply circuit includes: a transformer circuit, a power switch circuit, a primary side control circuit, an opto-coupler circuit, and a secondary side control circuit. The primary side control circuit determines whether an over voltage condition occurs, and further determines whether to generate an over voltage protection signal to turn OFF a power switch of the power switch circuit according to a rate of increase of a feedback signal and a control level, or according to the rate of increase of the feedback signal and a rate of change of a target control signal.
摘要翻译：本发明公开了一种具有可编程功能的反激式电源电路及其控制方法。回扫电源电路包括：变压器电路，电源开关电路，初级侧控制电路，光耦合器电路和次级侧控制电路。初级侧控制电路确定是否发生过电压状态，并且还根据反馈信号的增加率和控制电平来确定是否产生过电压保护信号以关断功率开关电路的电源开关，或根据反馈信号的增加速率和目标控制信号的变化率。

4. 发明申请

US20110068761A1 AVERAGE CURRENT REGULATOR AND DRIVER CIRCUIT THEREOF AND METHOD FOR REGULATING AVERAGE CURRENT 有权
标题翻译：平均电流调节器及其驱动电路及调节平均电流的方法
公开(公告)号：US20110068761A1
公开(公告)日：2011-03-24
申请号：US12878185
申请日：2010-09-09
申请人： An-Tung Chen , Isaac Y. Chen , Chien-Fu Tang
发明人： An-Tung Chen , Isaac Y. Chen , Chien-Fu Tang
IPC分类号： G05F1/00
CPC分类号： H02M3/156 , H02M2001/0009 , H05B33/0815 , Y02B20/347
摘要： The present invention discloses an average current regulator, a driver circuit of an average current regulator, and a method for regulating an average current. The average current regulator includes: a power stage including at least one power transistor which switches according to a pulse width modulation (PWM) signal to convert an input voltage to an output current; a feedback circuit coupled to the power stage, for generating a feedback signal; an ON-time controller coupled to the feedback circuit, for receiving the feedback signal and generating an ON-time signal according to the feedback signal and an average reference signal relating to a target average current; and a PWM controller, for generating the PWM signal according to the ON-time signal to regulate the average of the output current to the target average current.
摘要翻译：本发明公开了一种平均电流调节器，平均电流调节器的驱动电路和用于调节平均电流的方法。平均电流调节器包括：功率级，包括至少一个功率晶体管，其根据脉冲宽度调制（PWM）信号切换以将输入电压转换为输出电流; 耦合到功率级的反馈电路，用于产生反馈信号; 耦合到反馈电路的接通时间控制器，用于接收反馈信号并根据反馈信号和与目标平均电流相关的平均参考信号产生接通时间信号; 以及PWM控制器，用于根据接通时间信号产生PWM信号，以将输出电流的平均值调节到目标平均电流。

5. 发明授权

US08674554B2 Power off delay circuit and method, and audio system with power off delay 失效
标题翻译：断电延时电路及方法，以及具有断电延时的音响系统
公开(公告)号：US08674554B2
公开(公告)日：2014-03-18
申请号：US12818539
申请日：2010-06-18
申请人： Chi-Hua Lin , Chien-Fu Tang , Isaac Y Chen , An-Tung Chen
发明人： Chi-Hua Lin , Chien-Fu Tang , Isaac Y Chen , An-Tung Chen
IPC分类号： H02B1/24
CPC分类号： H02B1/24 , H04R3/007 , Y10T307/74 , Y10T307/766
摘要： A power off delay circuit includes a switch connected between an external power input terminal and an internal power supply terminal, a capacitor connected to the internal power supply terminal, and a hysteresis comparator to switch the switch according to the voltages of the external power input terminal and the internal power supply terminal. During on-time of the switch, the external power input terminal is connected to the internal power supply terminal and the capacitor can be charged by the external power source. When the switch is off, the capacitor provides electric power for an internal circuit. Application of the power off delay circuit to an audio system may eliminate the turn-off pops of the audio system.
摘要翻译：断电延迟电路包括连接在外部电源输入端子和内部电源端子之间的开关，连接到内部电源端子的电容器和滞后比较器，用于根据外部电力输入端子的电压来切换开关和内部电源端子。在接通时，外部电源输入端子连接到内部电源端子，电容器可以通过外部电源充电。当开关关闭时，电容为内部电路提供电力。将断电延迟电路应用于音频系统可以消除音频系统的关闭声音。

6. 发明授权

US08400127B2 Average current regulator and driver circuit thereof and method for regulating average current 有权
标题翻译：平均电流调节器及其驱动电路及调节平均电流的方法
公开(公告)号：US08400127B2
公开(公告)日：2013-03-19
申请号：US12878185
申请日：2010-09-09
申请人： An-Tung Chen , Isaac Y. Chen , Chien-Fu Tang
发明人： An-Tung Chen , Isaac Y. Chen , Chien-Fu Tang
IPC分类号： G05F1/40
CPC分类号： H02M3/156 , H02M2001/0009 , H05B33/0815 , Y02B20/347
摘要： The present invention discloses an average current regulator, a driver circuit of an average current regulator, and a method for regulating an average current. The average current regulator includes: a power stage including at least one power transistor which switches according to a pulse width modulation (PWM) signal to convert an input voltage to an output current; a feedback circuit coupled to the power stage, for generating a feedback signal; an ON-time controller coupled to the feedback circuit, for receiving the feedback signal and generating an ON-time signal according to the feedback signal and an average reference signal relating to a target average current; and a PWM controller, for generating the PWM signal according to the ON-time signal to regulate the average of the output current to the target average current.
摘要翻译：本发明公开了一种平均电流调节器，平均电流调节器的驱动电路和用于调节平均电流的方法。平均电流调节器包括：功率级，包括至少一个功率晶体管，其根据脉冲宽度调制（PWM）信号切换以将输入电压转换为输出电流; 耦合到功率级的反馈电路，用于产生反馈信号; 耦合到反馈电路的接通时间控制器，用于接收反馈信号并根据反馈信号和与目标平均电流相关的平均参考信号产生接通时间信号; 以及PWM控制器，用于根据接通时间信号产生PWM信号，以将输出电流的平均值调节到目标平均电流。

7. 发明申请

US20140055178A1 ADAPTIVE PHASE-SHIFTED SYNCHRONIZATION CLOCK GENERATION CIRCUIT AND METHOD FOR GENERATING PHASE-SHIFTED SYNCHRONIZATION CLOCK 审中-公开
标题翻译：自适应相位同步时钟产生电路及相位转换同步时钟的生成方法
公开(公告)号：US20140055178A1
公开(公告)日：2014-02-27
申请号：US14070518
申请日：2013-11-02
申请人： Isaac Chen , An-Tung Chen
发明人： Isaac Chen , An-Tung Chen
IPC分类号： H03K5/15
CPC分类号： H03K5/15073 , G06F1/04 , H02J3/01 , H02M2003/1586 , Y10T307/50 , Y10T307/707
摘要： The present invention discloses an adaptive phase-shifted synchronization clock generation circuit and a method for generating phase-shifted synchronization clock. The adaptive phase-shifted synchronization clock generation circuit includes: a current source generating a current which flows through a node to generate a node voltage on the node; a reverse-proportional voltage generator coupled to the node for generating a voltage which is reverse-proportional to the node voltage; a ramp generator receiving a synchronization input signal and generating a ramp signal; a comparator comparing the reverse-proportional voltage to the ramp signal; and a pulse generator for generating a clock signal according to an output from the comparator.
摘要翻译：本发明公开了一种自适应相移同步时钟产生电路和一种产生相移同步时钟的方法。自适应相移同步时钟生成电路包括：电流源，其产生流过节点的电流，以在节点上产生节点电压; 耦合到所述节点的反向比例电压发生器，用于产生与所述节点电压成反比的电压; 斜坡发生器接收同步输入信号并产生斜坡信号; 比较反向比例电压与斜坡信号的比较器; 以及用于根据比较器的输出产生时钟信号的脉冲发生器。

8. 发明申请

US20070064454A1 Circuit and method for soft start from a residual voltage 有权
标题翻译：从残余电压软启动的电路和方法
公开(公告)号：US20070064454A1
公开(公告)日：2007-03-22
申请号：US11487388
申请日：2006-07-17
申请人： Isaac Chen , An-Tung Chen , Liang-Pin Tai
发明人： Isaac Chen , An-Tung Chen , Liang-Pin Tai
IPC分类号： H02M1/00
CPC分类号： H02M1/36 , H02M3/156 , H02M2001/0025 , Y10S323/901
摘要： A circuit and method for soft start of a system compare a feedback signal produced from an output voltage of the system with a ramp signal to generate a comparison signal, and enables the system once the comparison signal indicating the ramp signal reaches the feedback signal, such that the output voltage becomes active from a residual voltage toward a target level.
摘要翻译：用于软启动的系统的电路和方法将从系统的输出电压产生的反馈信号与斜坡信号进行比较，以产生比较信号，并且一旦指示斜坡信号的比较信号达到反馈信号，使能系统，输出电压从残余电压向目标电平变为有效。

9. 发明申请

US20110280353A1 Adaptive phase-shifted synchronization clock generation circuit and method for generating phase-shifted synchronization clock 有权
标题翻译：自适应相移同步时钟生成电路和产生相移同步时钟的方法
公开(公告)号：US20110280353A1
公开(公告)日：2011-11-17
申请号：US12930941
申请日：2011-01-20
申请人： Isaac Chen , An-Tung Chen
发明人： Isaac Chen , An-Tung Chen
IPC分类号： H04L7/00
CPC分类号： H03K5/15073 , G06F1/04 , H02J3/01 , H02M2003/1586 , Y10T307/50 , Y10T307/707
摘要： The present invention discloses an adaptive phase-shifted synchronization clock generation circuit and a method for generating phase-shifted synchronization clock. The adaptive phase-shifted synchronization clock generation circuit includes: a current source generating a current which flows through a node to generate a node voltage on the node; a reverse-proportional voltage generator coupled to the node for generating a voltage which is reverse-proportional to the node voltage; a ramp generator receiving a synchronization input signal and generating a ramp signal; a comparator comparing the reverse-proportional voltage to the ramp signal; and a pulse generator for generating a clock signal according to an output from the comparator.
摘要翻译：本发明公开了一种自适应相移同步时钟产生电路和一种产生相移同步时钟的方法。自适应相移同步时钟生成电路包括：电流源，其产生流过节点的电流，以在节点上产生节点电压; 耦合到所述节点的反向比例电压发生器，用于产生与所述节点电压成反比的电压; 斜坡发生器接收同步输入信号并产生斜坡信号; 比较反向比例电压与斜坡信号的比较器; 以及用于根据比较器的输出产生时钟信号的脉冲发生器。

10. 发明授权

US09008251B2 Adaptive phase-shifted synchronization clock generation circuit and method for generating phase-shifted synchronization clock 有权
标题翻译：自适应相移同步时钟生成电路和产生相移同步时钟的方法
公开(公告)号：US09008251B2
公开(公告)日：2015-04-14
申请号：US14070518
申请日：2013-11-02
申请人： Isaac Chen , An-Tung Chen
发明人： Isaac Chen , An-Tung Chen
IPC分类号： G06F1/04 , H02M3/156 , H03K5/15 , H02J3/01 , H02M3/158
CPC分类号： H03K5/15073 , G06F1/04 , H02J3/01 , H02M2003/1586 , Y10T307/50 , Y10T307/707
摘要： The present invention discloses an adaptive phase-shifted synchronization clock generation circuit and a method for generating phase-shifted synchronization clock. The adaptive phase-shifted synchronization clock generation circuit includes: a current source generating a current which flows through a node to generate a node voltage on the node; a reverse-proportional voltage generator coupled to the node for generating a voltage which is reverse-proportional to the node voltage; a ramp generator receiving a synchronization input signal and generating a ramp signal; a comparator comparing the reverse-proportional voltage to the ramp signal; and a pulse generator for generating a clock signal according to an output from the comparator.
摘要翻译：本发明公开了一种自适应相移同步时钟产生电路和一种产生相移同步时钟的方法。自适应相移同步时钟生成电路包括：电流源，其产生流过节点的电流，以在节点上产生节点电压; 耦合到所述节点的反向比例电压发生器，用于产生与所述节点电压成反比的电压; 斜坡发生器接收同步输入信号并产生斜坡信号; 比较反向比例电压与斜坡信号的比较器; 以及用于根据比较器的输出产生时钟信号的脉冲发生器。

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