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1. 发明授权

US07660932B2 Composing on-chip interconnects with configurable interfaces 有权
标题翻译：组合片上互连与可配置接口
公开(公告)号：US07660932B2
公开(公告)日：2010-02-09
申请号：US12022912
申请日：2008-01-30
申请人： Chien Chun Chou , Wolf-Dietrich Weber , Drew E. Wingard
发明人： Chien Chun Chou , Wolf-Dietrich Weber , Drew E. Wingard
IPC分类号： G06F13/00
CPC分类号： H04L69/18 , G06F15/7825
摘要： Embodiments of apparatuses, systems, and methods are described for a machine-readable medium having instructions stored thereon, which, when executed by a machine, to cause the machine to generate a representation of an apparatus. The apparatus includes a bridge agent, a first interconnect, and a second interconnect. The bridge agent is configured by bridge control signals to control transmission of a communication between the first interconnect and the second interconnect. The representation may be a sequence of instructions written in a programming language to mimic in a computer simulation environment attributes derived from a projected fabricated hardware instance of the apparatus.
摘要翻译：对于具有存储在其上的指令的机器可读介质描述了装置，系统和方法的实施例，当由机器执行时，该机器可读介质使机器产生装置的表示。该装置包括桥接器，第一互连和第二互连。桥接代理由桥控制信号配置，以控制第一互连和第二互连之间的通信的传输。该表示可以是以编程语言编写的指令序列，以在计算机模拟环境中模仿从该装置的投影制造的硬件实例导出的属性。

2. 发明申请

US20100211935A1 METHOD AND APPARATUS FOR ESTABLISHING A QUALITY OF SERVICE MODEL 有权
标题翻译：建立质量服务模式的方法与装置
公开(公告)号：US20100211935A1
公开(公告)日：2010-08-19
申请号：US12706656
申请日：2010-02-16
申请人： Wolf-Dietrich Weber , Chien-Chun Chou , Drew E. Wingard
发明人： Wolf-Dietrich Weber , Chien-Chun Chou , Drew E. Wingard
IPC分类号： G06F9/44 , G06F9/46 , G06F12/00
CPC分类号： H04L47/10 , H04L47/2425 , H04L47/70 , H04L47/805 , H04L47/821 , H04L47/827
摘要： In general, methods and apparatus for implementing a Quality of Service (QoS) model are disclosed. A Quality of Service (QoS) contract with an initiating network device may be satisfied. A request may be received from the initiating network device in a first time less than or equal to an ordinal number times an arrival interval. The ordinal number signifies a position of the request among a group of requests. The request that has been serviced may be returned to the initiator in a second time less than or equal to a constant term plus the ordinal number times a service interval.
摘要翻译：通常，公开了实现服务质量（QoS）模型的方法和装置。可以满足与发起网络设备的服务质量（QoS）合同。可以在起始网络设备中的第一次小于等于序号到达间隔的时间来接收请求。序号表示一组请求中请求的位置。已经服务的请求可以在小于或等于常数项加上序数与服务间隔倍数的第二时间返回给启动器。

3. 发明授权

US08504992B2 Method and apparatus for establishing a quality of service model 有权
标题翻译：建立服务质量模型的方法和装置
公开(公告)号：US08504992B2
公开(公告)日：2013-08-06
申请号：US12706656
申请日：2010-02-16
申请人： Wolf-Dietrich Weber , Chien-Chun Chou , Drew E. Wingard
发明人： Wolf-Dietrich Weber , Chien-Chun Chou , Drew E. Wingard
IPC分类号： G06F9/44 , G06F15/173 , G06F13/00 , H04L12/28
CPC分类号： H04L47/10 , H04L47/2425 , H04L47/70 , H04L47/805 , H04L47/821 , H04L47/827
摘要： In general, methods and apparatus for implementing a Quality of Service (QoS) model are disclosed. A Quality of Service (QoS) contract with an initiating network device may be satisfied. A request may be received from the initiating network device in a first time less than or equal to an ordinal number times an arrival interval. The ordinal number signifies a position of the request among a group of requests. The request that has been serviced may be returned to the initiator in a second time less than or equal to a constant term plus the ordinal number times a service interval.
摘要翻译：通常，公开了实现服务质量（QoS）模型的方法和装置。可以满足与发起网络设备的服务质量（QoS）合同。可以在起始网络设备中的第一次小于或等于序号到达间隔的时间来接收请求。序号表示一组请求中请求的位置。已经服务的请求可以在小于或等于常数项加上序数与服务间隔倍数的第二时间返回给启动器。

4. 发明申请

US20080140903A1 COMPOSING ON-CHIP INTERCONNECTS WITH CONFIGURABLE INTERFACES 有权
标题翻译：使用可配置的接口组合片上互连
公开(公告)号：US20080140903A1
公开(公告)日：2008-06-12
申请号：US12022912
申请日：2008-01-30
申请人： Chien-Chun Chou , Wolf-Dietrich Weber , Drew E. Wingard
发明人： Chien-Chun Chou , Wolf-Dietrich Weber , Drew E. Wingard
IPC分类号： G06F13/36
CPC分类号： H04L69/18 , G06F15/7825
摘要： Embodiments of apparatuses, systems, and methods are described for a machine-readable medium having instructions stored thereon, which, when executed by a machine, to cause the machine to generate a representation of an apparatus. The apparatus includes a bridge agent, a first interconnect, and a second interconnect. The bridge agent is configured by bridge control signals to control transmission of a communication between the first interconnect and the second interconnect. The representation may be a sequence of instructions written in a programming language to mimic in a computer simulation environment attributes derived from a projected fabricated hardware instance of the apparatus.
摘要翻译：对于具有存储在其上的指令的机器可读介质描述了装置，系统和方法的实施例，当由机器执行时，该机器可读介质使机器产生装置的表示。该装置包括桥接器，第一互连和第二互连。桥接代理由桥控制信号配置，以控制第一互连和第二互连之间的通信的传输。该表示可以是以编程语言编写的指令序列，以在计算机模拟环境中模仿从该装置的投影制造的硬件实例导出的属性。

5. 发明授权

US06785753B2 Method and apparatus for response modes in pipelined environment 有权
标题翻译：流水线环境中的响应模式的方法和装置
公开(公告)号：US06785753B2
公开(公告)日：2004-08-31
申请号：US09872126
申请日：2001-06-01
申请人： Wolf-Dietrich Weber , Jay S. Tomlinson , Drew E. Wingard
发明人： Wolf-Dietrich Weber , Jay S. Tomlinson , Drew E. Wingard
IPC分类号： G06F1342
CPC分类号： G06F13/4226
摘要： A pipelined network is disclosed which provides for at least one mode to control the state of a response flag and when the target device is unable to respond to an initiator device request.
摘要翻译：公开了一种流水线网络，其提供至少一种模式来控制响应标志的状态，并且当目标设备不能响应发起者设备请求时。

6. 发明授权

US07793345B2 Method and apparatus for a configurable protection architecture for on-chip systems 有权
标题翻译：用于片上系统的可配置保护架构的方法和装置
公开(公告)号：US07793345B2
公开(公告)日：2010-09-07
申请号：US11237038
申请日：2005-09-27
申请人： Wolf-Dietrich Weber , Drew E. Wingard , Stephen W. Hamilton , Frank Seigneret
发明人： Wolf-Dietrich Weber , Drew E. Wingard , Stephen W. Hamilton , Frank Seigneret
IPC分类号： G06F7/04 , G06F12/00 , G06F12/14 , G06F13/00 , G06F17/30 , G06F11/00 , G06F12/04 , G06F12/16 , G11C7/00 , G08B23/00
CPC分类号： G06F21/78 , G06F12/10 , Y02D10/13
摘要： Various methods and apparatuses of protection mechanism are described. A target intellectual property block may field and service requests from an initiator intellectual property block in a system-on-chip network. The target intellectual property block has an associated protection mechanism with logic configured to restrict access for the requests to the target intellectual property block. The request's access is restricted based on access permissions associated with a region within the target intellectual property block and attributes of the request trying to access that region.
摘要翻译：描述了各种保护机制的方法和装置。目标知识产权块可以在芯片上系统网络中来自发起者知识产权块的请求。目标知识产权块具有相关联的保护机制，其逻辑被配置为将请求的访问限制到目标知识产权块。基于与目标知识产权块内的区域相关联的访问权限和尝试访问该区域的请求的属性，请求的访问受到限制。

7. 发明授权

US07165094B2 Communications system and method with non-blocking shared interface 有权
标题翻译：具有非阻塞共享接口的通信系统和方法
公开(公告)号：US07165094B2
公开(公告)日：2007-01-16
申请号：US09802405
申请日：2001-03-09
申请人： Wolf-Dietrich Weber , Richard Aras , Lisa A. Robinson , Geert P. Rosseel , Jay S. Tomlinson , Drew E. Wingard
发明人： Wolf-Dietrich Weber , Richard Aras , Lisa A. Robinson , Geert P. Rosseel , Jay S. Tomlinson , Drew E. Wingard
IPC分类号： G06F15/16
CPC分类号： G06F13/14 , G06F9/54
摘要： A communication system. One embodiment includes at least two functional blocks, wherein an first functional block communicates with a second functional block by establishing a connection. A connection is a logical state in which data may pass between the first functional block and the second functional block. One embodiment includes a bus coupled to each of the functional blocks and configured to carry a plurality of signals. The plurality of signals includes a thread identifier that indicates a transaction stream that the data transfer is part of and a busy signal identified by the thread identifier. The busy signal is issued by the target functional block when resources will be unavailable to perform a transfer.
摘要翻译：通讯系统一个实施例包括至少两个功能块，其中第一功能块通过建立连接与第二功能块通信。连接是数据可以在第一功能块和第二功能块之间通过的逻辑状态。一个实施例包括耦合到每个功能块并被配置为承载多个信号的总线。多个信号包括指示数据传输是其中一部分的事务流的线程标识符和由线程标识符标识的忙信号。当资源不可用时执行传输，目标功能块发出忙信号。

8. 发明授权

US06330225B1 Communication system and method for different quality of service guarantees for different data flows 有权
标题翻译：不同数据流量的不同服务质量的通信系统和方法保证
公开(公告)号：US06330225B1
公开(公告)日：2001-12-11
申请号：US09580031
申请日：2000-05-26
申请人： Wolf-Dietrich Weber , Richard Aras , Drew E. Wingard
发明人： Wolf-Dietrich Weber , Richard Aras , Drew E. Wingard
IPC分类号： H04J316
CPC分类号： H04L47/805 , H04J3/1682 , H04L47/10 , H04L47/15 , H04L47/70 , H04L47/827
摘要： A system and method for providing service guarantees for data flows between an initiator component and a target component. For each data flow, a set of channels is selected to carry the data flow from initiator to target. The individual performance guarantees of the selected channels are aligned to be uniform in units and the individual guarantees are aggregated to provide an end-to-end service guarantee for a particular flow.
摘要翻译：一种用于为启动器组件和目标组件之间的数据流提供服务保证的系统和方法。对于每个数据流，选择一组通道来承载从启动器到目标的数据流。所选频道的单个性能保证被统一为单位，并且个体保证被聚合以为特定流提供端到端服务保证。

9. 发明授权

US07296105B2 Method and apparatus for configuring an interconnect to implement arbitration 有权
标题翻译：用于配置互连以实施仲裁的方法和装置
公开(公告)号：US07296105B2
公开(公告)日：2007-11-13
申请号：US10678380
申请日：2003-10-03
申请人： Wolf-Dietrich Weber , Drew E. Wingard
发明人： Wolf-Dietrich Weber , Drew E. Wingard
IPC分类号： G06F15/16
CPC分类号： G06F13/364 , H04L12/40032 , H04L12/403 , H04L12/4625 , Y02D10/14
摘要： Various methods and apparatuses are described in which an interconnect couples to a plurality of initiator network resources and a plurality of target network resources. The interconnect may include a first stage of circuitry, a second stage of circuitry, and an arbitration controller. The first stage of circuitry receives incoming transactions from the plurality of initiator network resources. The second stage of circuitry passes outgoing transactions to the plurality of target network resources connecting to the interconnect. The arbitration controller arbitrates transactions from the plurality of initiator network resources destined to one or more of the target network resources. The target network resources supply their availability to service a transaction to the arbitration controller. The arbitration controller implements an arbitration policy that filters out transactions from the arbitration process those transactions from initiator network resources destine to target network resources that are currently not available to service a transaction.
摘要翻译：描述各种方法和装置，其中互连耦合到多个发起者网络资源和多个目标网络资源。互连可以包括第一级电路，第二级电路和仲裁控制器。电路的第一阶段从多个发起者网络资源接收传入的事务。电路的第二阶段将输出事务传递到连接到互连的多个目标网络资源。仲裁控制器仲裁来自指定给一个或多个目标网络资源的多个发起者网络资源的事务。目标网络资源将其可用性提供给仲裁控制器。仲裁控制器实施仲裁策略，从仲裁过程中过滤出来自发起者网络资源的那些事务指向当前不可用于服务于事务的网络资源的目标网络资源。

10. 发明申请

US20100057400A1 METHOD AND SYSTEM TO MONITOR, DEBUG, AND ANALYZE PERFORMANCE OF AN ELECTRONIC DESIGN 有权
标题翻译：监测，调试和分析电子设计性能的方法和系统
公开(公告)号：US20100057400A1
公开(公告)日：2010-03-04
申请号：US12204156
申请日：2008-09-04
申请人： Chien-Chun Chou , Stephen W. Hamilton , Drew E. Wingard , Pascal Chauvet
发明人： Chien-Chun Chou , Stephen W. Hamilton , Drew E. Wingard , Pascal Chauvet
IPC分类号： G21C17/00
CPC分类号： G06F11/3466 , G06F11/3471 , G06F11/348 , G06F2201/86 , G06F2201/87 , G06F2201/88
摘要： Various methods and apparatuses are described that provide instrumentation and analysis of an electronic design. A performance monitoring apparatus may be located on an interconnect of a fabricated integrated circuit. An event measurement module (EM) includes an event generator sub-module that generates monitoring events and event measurements associated with transactions between initiator intellectual property (IP) cores and target IP cores over the interconnect. The EM further includes a software visible register block that provides software access for controlling the EM on which one or more transactions to monitor and to configure one or more parameters associated with that transaction to track. The EM further includes a filtering sub-module that selects transactions to be monitored based on information received from the software. The performance counter module aggregates events and event measurements received from the EM into quantities of performance metrics associated with transactions between the IP cores over the interconnect.
摘要翻译：描述了提供电子设计的仪器和分析的各种方法和装置。性能监视装置可以位于所制造的集成电路的互连上。事件测量模块（EM）包括一个事件发生器子模块，该事件发生器子模块通过互连产生与发起者知识产权（IP）核心和目标IP内核之间的事务相关联的监视事件和事件测量。 EM还包括软件可见寄存器块，其提供用于控制EM监视的一个或多个事务的软件访问以及配置与该事务相关联的一个或多个参数以进行跟踪。 EM还包括一个过滤子模块，该过滤子模块根据从软件接收的信息来选择要监视的事务。性能计数器模块将从EM接收到的事件和事件测量聚合到与互连上的IP内核之间的事务相关联的性能度量数量。

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