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    • 2. 发明申请
    • Nonvolatile flash memory and method of operating the same
    • 非易失闪存及其操作方法
    • US20050270850A1
    • 2005-12-08
    • US10861392
    • 2004-06-07
    • Lee WangDaniel HuangHsin LinRoget Chang
    • Lee WangDaniel HuangHsin LinRoget Chang
    • G11C11/34G11C16/04
    • G11C16/0416G11C16/3477G11C2216/10
    • A nonvolatile memory and a method of operating the same are proposed. The nonvolatile memory has single-gate memory cells, wherein a structure of a transistor and a capacitor is embedded in a semiconductor substrate. The transistor comprises a first conducting gate stacked on the surface of a dielectric with doped regions formed at two sides thereof as a source and a drain. The capacitor comprises a doped region, a dielectric stacked thereon, and a second conducting gate. The conducting gates of the capacitor and the transistor are electrically connected together to form a single floating gate of the memory cell. The semiconductor substrate is p-type or n-type. Besides, a back-bias program write-in and related erase and readout operation ways are proposed for the single-gate memory cells.
    • 提出了一种非易失性存储器及其操作方法。 非易失性存储器具有单栅极存储单元,其中晶体管和电容器的结构嵌入在半导体衬底中。 晶体管包括堆叠在电介质的表面上的第一导电栅,其两侧形成有掺杂区域作为源极和漏极。 电容器包括掺杂区域,堆叠在其上的电介质和第二导电栅极。 电容器和晶体管的导通栅极电连接在一起以形成存储单元的单个浮置栅极。 半导体衬底是p型或n型。 此外,针对单栅极存储器单元提出了背偏置程序写入和相关的擦除和读出操作方式。
    • 3. 发明申请
    • High-speed low-voltage programming and self-convergent high-speed low-voltage erasing schemes for EEPROM
    • 用于EEPROM的高速低压编程和自适应高速低电压擦除方案
    • US20070158733A1
    • 2007-07-12
    • US11327436
    • 2006-01-09
    • Daniel HuangLee WangHsin LinRoget Chang
    • Daniel HuangLee WangHsin LinRoget Chang
    • H01L29/788
    • H01L29/7885G11C16/0416G11C16/10G11C16/14
    • The present invention provides a high-speed low-voltage programming scheme and self-convergent high-speed low-voltage erasing schemes for Electrically Erasable Programmable Read-Only Memories (EEPROM). For the N-type Field Effect Transistor (NFET) based NVM programming, an elevated source voltage to the substrate can achieve high efficient Drain-Avalanche-Hot-Electron Injection (DAHEI) into the floating gate resulting in high-speed and low-voltage operations. The self-convergent and low-voltage erasing can be achieved by applying Drain-Avalanche-Hot Hole Injection (DAHHI) with the conditions of restricted maximum drain current and a moderate control gate voltage enough to turn on the NFET. For the p-type FET (PFET) based EEPROM programming, a negative source voltage relative to the substrate can achieve high efficient Drain-Avalanche-Hot-Hole Injection (DAHHI) into the floating gate resulting in high-speed and low voltage operations. The self-convergent and low voltage erasing can be achieved by applying Drain-Avalanche-Hot-Electron Injection (DAHEI) with the conditions of restricted maximum magnitude of drain current and a negative moderate control gate voltage enough to turn on the PFET.
    • 本发明提供了用于电可擦除可编程只读存储器(EEPROM)的高速低压编程方案和自会聚高速低电压擦除方案。 对于基于N型场效应晶体管(NFET)的NVM编程,提高到衬底的源极电压可以实现高效率的漏极 - 雪崩 - 热电子注入(DAHEI)到浮动栅极,从而产生高速和低电压 操作。 通过应用漏极 - 雪崩 - 热孔注入(DAHHI),可以实现自收敛和低电压擦除,其条件是限制最大漏极电流和适度的控制栅极电压足以导通NFET。 对于基于P型FET(PFET)的EEPROM编程,相对于衬底的负电源电压可以实现高效率的漏 - 雪 - 热孔注入(DAHHI)到浮栅中,从而实现高速和低电压操作。 通过施加漏极 - 雪崩热电子注入(DAHEI),限制漏极电流的最大值限制和足够的负的中等控制栅极电压来打开PFET,可实现自收敛和低电压擦除。