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1. 发明授权

US08378756B2 Drive loop for MEMS oscillator 有权
标题翻译： MEMS振荡器的驱动环路
公开(公告)号：US08378756B2
公开(公告)日：2013-02-19
申请号：US12782064
申请日：2010-05-18
申请人： Ming-Chieh Huang , Chiang Pu , Chan-Hong Chern , Chih-Chang Lin , Yuwen Swei
发明人： Ming-Chieh Huang , Chiang Pu , Chan-Hong Chern , Chih-Chang Lin , Yuwen Swei
IPC分类号： H03B5/30 , G01C19/00
CPC分类号： H03B5/30
摘要： Some embodiments regard a method comprising: generating a current according to a movement of the MEMS device; the movement is controlled by a control signal; generating a peak voltage according to the current; and adjusting the control signal when the peak voltage is out of a predetermined range.
摘要翻译：一些实施例涉及一种方法，包括：根据MEMS装置的移动产生电流; 移动由控制信号控制; 根据电流产生峰值电压; 以及当峰值电压超出预定范围时调节控制信号。

2. 发明授权

US08115545B2 Automatic level control 有权
标题翻译：自动电平控制
公开(公告)号：US08115545B2
公开(公告)日：2012-02-14
申请号：US13177958
申请日：2011-07-07
申请人： Chiang Pu , Ming-Chieh Huang , Chan-Hong Chern , Tien-Chun Yang
发明人： Chiang Pu , Ming-Chieh Huang , Chan-Hong Chern , Tien-Chun Yang
IPC分类号： H03F1/36
CPC分类号： G01C19/5776
摘要： Some embodiments regard a circuit comprising: a high voltage transistor providing a resistance; an amplifier configured to receive a current and to convert the current to a first voltage that is used in a loop creating the current; and an automatic level control circuit that, based on an AC amplitude of the first voltage, adjusts a second voltage at a gate of the high voltage transistor and thereby adjusts the resistance and the first voltage; wherein the automatic level control circuit is configured to adjust the first voltage toward the first reference voltage if the first voltage differs from a first reference voltage.
摘要翻译：一些实施例涉及一种电路，包括：提供电阻的高压晶体管; 放大器，被配置为接收电流并将电流转换成在产生电流的环路中使用的第一电压; 以及自动电平控制电路，其基于所述第一电压的交流振幅调整所述高电压晶体管的栅极处的第二电压，从而调整所述电阻和所述第一电压; 其中所述自动电平控制电路被配置为如果所述第一电压与第一参考电压不同，则将所述第一电压调整为朝向所述第一参考电压。

3. 发明授权

US08766613B2 Method of operating voltage regulator 有权
标题翻译：操作电压调节器的方法
公开(公告)号：US08766613B2
公开(公告)日：2014-07-01
申请号：US13744037
申请日：2013-01-17
申请人： Chan-Hong Chern , Tzu-Ching Chang , Min-Shueh Yuan , Yuwen Swei , Chih-Chang Lin , Chiang Pu , Ming-Chieh Huang , Kuoyuan Hsu
发明人： Chan-Hong Chern , Tzu-Ching Chang , Min-Shueh Yuan , Yuwen Swei , Chih-Chang Lin , Chiang Pu , Ming-Chieh Huang , Kuoyuan Hsu
IPC分类号： G05F1/44
CPC分类号： H02M3/158 , G05F1/44 , G05F1/56
摘要： A method of operating a voltage regulator circuit includes generating a control signal by an amplifier of the voltage regulator circuit. The control signal is generated based on a reference signal at an inverting input of the amplifier and a feedback signal at a non-inverting input of the amplifier. A driving current flowing toward an output node of the voltage regulator circuit is generated by a driver responsive to the control signal, and the driver is coupled between a first power node and the output node. The feedback signal is generated responsive to a voltage level at the output node. A transistor, coupled between the output node and a second power node, is caused to operate in saturation mode during a period while the voltage regulator circuit is operating.
摘要翻译：一种操作电压调节器电路的方法包括由稳压器电路的放大器产生控制信号。控制信号基于放大器的反相输入处的参考信号和放大器的非反相输入端的反馈信号而产生。通过响应于控制信号的驱动器产生朝向电压调节器电路的输出节点流动的驱动电流，并且驱动器耦合在第一功率节点和输出节点之间。响应于输出节点处的电压电平产生反馈信号。耦合在输出节点和第二功率节点之间的晶体管在电压调节器电路工作期间的一段时间内使其工作在饱和模式。

4. 发明申请

US20110285445A1 DRIVE LOOP FOR MEMS OSCILLATOR 有权
标题翻译：用于MEMS振荡器的驱动环
公开(公告)号：US20110285445A1
公开(公告)日：2011-11-24
申请号：US12782064
申请日：2010-05-18
申请人： Ming-Chieh Huang , Chiang Pu , Chan-Hong Chern , Chih-Chang Lin , Yuwen Swei
发明人： Ming-Chieh Huang , Chiang Pu , Chan-Hong Chern , Chih-Chang Lin , Yuwen Swei
IPC分类号： H03L5/00 , H03B5/30 , H02K33/00
CPC分类号： H03B5/30
摘要： Some embodiments regard a method comprising: generating a current according to a movement of the MEMS device; the movement is controlled by a control signal; generating a peak voltage according to the current; and adjusting the control signal when the peak voltage is out of a predetermined range.
摘要翻译：一些实施例涉及一种方法，包括：根据MEMS装置的移动产生电流; 移动由控制信号控制; 根据电流产生峰值电压; 以及当峰值电压超出预定范围时调节控制信号。

5. 发明授权

US08896352B2 Drivers having T-coil structures 有权
标题翻译：驱动器具有T型线圈结构
公开(公告)号：US08896352B2
公开(公告)日：2014-11-25
申请号：US13278742
申请日：2011-10-21
申请人： Ming-Chieh Huang , Tao Wen Chung , Chan-Hong Chern , Chih-Chang Lin , Yuwen Swei , Chiang Pu
发明人： Ming-Chieh Huang , Tao Wen Chung , Chan-Hong Chern , Chih-Chang Lin , Yuwen Swei , Chiang Pu
IPC分类号： H03K3/00
CPC分类号： H03H11/44 , H01S5/0427 , H04B10/504
摘要： A driver includes a first driver stage having at least one input node and at least one first output node. The first driver stage includes a T-coil structure that is disposed adjacent to the at least one first output node. The T-coil structure includes a first set of inductors each being operable to provide a first inductance. A second set of inductors are electrically coupled with the first set of inductors in a parallel fashion. The second set of inductors each are operable to provide a second inductance. A second driver stage is electrically coupled with the first driver stage.
摘要翻译：驱动器包括具有至少一个输入节点和至少一个第一输出节点的第一驱动器级。第一驱动级包括邻近于至少一个第一输出节点设置的T型线圈结构。 T型线圈结构包括第一组电感器，每个电感器可操作以提供第一电感。第二组电感器以并行方式与第一组电感器电耦合。第二组电感器可操作以提供第二电感。第二驱动级与第一驱动器级电耦合。

6. 发明授权

US08369172B2 Integrated circuits for providing clock periods and operating methods thereof 有权
标题翻译：用于提供时钟周期的集成电路及其操作方法
公开(公告)号：US08369172B2
公开(公告)日：2013-02-05
申请号：US12844204
申请日：2010-07-27
申请人： Chiang Pu , Ming-Chieh Huang , Chan-Hong Chern
发明人： Chiang Pu , Ming-Chieh Huang , Chan-Hong Chern
IPC分类号： G11C7/00
CPC分类号： G05F1/10 , G11C7/22 , G11C7/222 , G11C11/406 , G11C11/40615 , G11C11/40626 , G11C2211/4065
摘要： An integrated circuit includes a capacitor. A switch is electrically coupled with the capacitor in a parallel fashion. A comparator includes a first input node, a second input node, and an output node. The second input node is electrically coupled with a first plate of the capacitor. The output node is electrically coupled with the switch. A transistor is electrically coupled with a second plate of the capacitor. A circuit is electrically coupled with a gate of the transistor. The circuit is configured to provide a bias voltage to the gate of the transistor so as to control a current that is supplied to charge the capacitor.
摘要翻译：集成电路包括电容器。开关以并联方式与电容器电耦合。比较器包括第一输入节点，第二输入节点和输出节点。第二输入节点与电容器的第一板电耦合。输出节点与开关电耦合。晶体管与电容器的第二板电耦合。电路与晶体管的栅极电耦合。电路被配置为向晶体管的栅极提供偏置电压，以便控制供给电容器充电的电流。

7. 发明授权

US08705308B2 Circuit and method for generating clock signal 有权
标题翻译：用于产生时钟信号的电路和方法
公开(公告)号：US08705308B2
公开(公告)日：2014-04-22
申请号：US13737624
申请日：2013-01-09
申请人： Chiang Pu , Ming-Chieh Huang , Chan-Hong Chern
发明人： Chiang Pu , Ming-Chieh Huang , Chan-Hong Chern
IPC分类号： G11C7/00
CPC分类号： G05F1/10 , G11C7/22 , G11C7/222 , G11C11/406 , G11C11/40615 , G11C11/40626 , G11C2211/4065
摘要： A circuit includes a comparator, a first circuit, and a second circuit. The comparator includes a first input node, a second input node, and an output node. The first circuit is configured to generate a temperature-dependent reference current at the second input node of the comparator. The second circuit is coupled with the second input node of the comparator. The second circuit is configured to increase a voltage level at the second input node of the comparator in response to the temperature-dependent reference current when a signal at the output node of the comparator indicates a first comparison result, and decrease the voltage level at the second input node of the comparator when the signal at the output node of the comparator indicates a second comparison result.
摘要翻译：电路包括比较器，第一电路和第二电路。比较器包括第一输入节点，第二输入节点和输出节点。第一电路被配置为在比较器的第二输入节点处产生与温度相关的参考电流。第二电路与比较器的第二输入节点耦合。第二电路被配置为当比较器的输出节点处的信号指示第一比较结果时，响应于温度相关的参考电流来增加比较器的第二输入节点处的电压电平，并且降低电压电平当比较器的输出节点处的信号指示第二比较结果时，比较器的第二输入节点。

8. 发明授权

US08378654B2 Voltage regulator with high accuracy and high power supply rejection ratio 有权
标题翻译：电压调节器具有高精度和高电源抑制比
公开(公告)号：US08378654B2
公开(公告)日：2013-02-19
申请号：US12750260
申请日：2010-03-30
申请人： Chan-Hong Chern , Tzu Ching Chang , Min-Shueh Yuan , Yuwen Swei , Chih-Chang Lin , Chiang Pu , Ming-Chieh Huang , Kuoyuan Hsu
发明人： Chan-Hong Chern , Tzu Ching Chang , Min-Shueh Yuan , Yuwen Swei , Chih-Chang Lin , Chiang Pu , Ming-Chieh Huang , Kuoyuan Hsu
IPC分类号： G05F1/44
CPC分类号： H02M3/158 , G05F1/44 , G05F1/56
摘要： A voltage regulator circuit with high accuracy and Power Supply Rejection Ratio (PSRR) is provided. In one embodiment, an op-amp with a voltage reference input to an inverting input has the first output connected to a PMOS transistor's gate. The PMOS transistor's source and drain are each connected to the power supply and the voltage regulator output. The voltage regulator output is connected to an NMOS transistor biased in saturation mode and a series of two resistors. The non-inverting input of the op-amp is connected in between the two resistors for the first feedback loop. The op-amp's second output is connected to the gate of the NMOS transistor through an AC-coupling capacitor for the second feedback loop. The op-amp's first output can be connected to the power supply voltage through a capacitor to further improve high frequency PSRR. In another embodiment, the role of PMOS and NMOS transistors is reversed.
摘要翻译：提供了具有高精度和电源抑制比（PSRR）的稳压电路。在一个实施例中，具有到反相输入的电压参考输入的运算放大器具有连接到PMOS晶体管的栅极的第一输出。 PMOS晶体管的源极和漏极各自连接到电源和稳压器输出。电压调节器输出连接到偏置在饱和模式的NMOS晶体管和一系列两个电阻。运算放大器的非反相输入端连接在第一个反馈回路的两个电阻之间。运算放大器的第二个输出通过用于第二反馈回路的交流耦合电容器连接到NMOS晶体管的栅极。运算放大器的第一个输出可以通过电容连接到电源电压，以进一步提高高频PSRR。在另一个实施例中，PMOS和NMOS晶体管的作用相反。

9. 发明授权

US08884665B2 Multiple-phase clock generator 有权
标题翻译：多相时钟发生器
公开(公告)号：US08884665B2
公开(公告)日：2014-11-11
申请号：US13084817
申请日：2011-04-12
申请人： Chih-Chang Lin , Chan-Hong Chern , Ming-Chieh Huang , Tao Wen Chung
发明人： Chih-Chang Lin , Chan-Hong Chern , Ming-Chieh Huang , Tao Wen Chung
IPC分类号： H03B19/00 , H03K5/15
CPC分类号： H03K5/15013
摘要： A multiple-phase clock generator includes at least one stage of dividers. A clock signal is supplied as a first stage clock input to dividers in a first stage of dividers. An N-th stage includes 2N dividers, where N is a positive integer number. Each divider in the first stage is configured to divide a first clock frequency of the first stage clock input by 2 to provide a first stage output. Each divider in the N-th stage is configured to divide an N-th clock frequency of an N-th stage clock input by 2 to provide an N-th stage output. The N-th stage outputs from the dividers in the N-th stage provide 2N-phase clock signals that are equally distributed with a same phase difference between adjacent phase clock signals.
摘要翻译：多相时钟发生器包括至少一个分频器级。时钟信号作为第一级时钟输入提供给分频器的第一级中的分频器。第N级包括2N个分频器，其中N是正整数。第一级中的每个分频器被配置为将第一级时钟输入的第一时钟频率除以2以提供第一级输出。第N级中的每个除法器被配置为将输入的第N级时钟的第N个时钟频率除以2以提供第N级输出。在第N级的分频器的第N级输出提供2N相位时钟信号，它们在相邻的相位时钟信号之间以相同的相位差均匀分布。

10. 发明授权

US08872592B2 High-speed transimpedance amplifier 有权
标题翻译：高速互阻放大器
公开(公告)号：US08872592B2
公开(公告)日：2014-10-28
申请号：US13527365
申请日：2012-06-19
申请人： Tsung-Ching Huang , Chan-Hong Chern , Tao Wen Chung , Ming-Chieh Huang , Chih-Chang Lin
发明人： Tsung-Ching Huang , Chan-Hong Chern , Tao Wen Chung , Ming-Chieh Huang , Chih-Chang Lin
IPC分类号： H03F3/08
CPC分类号： H03F3/082 , H03F1/0205 , H03F3/08 , H03F3/3022 , H03F3/45179 , H03F3/45183 , H03F2200/216 , H03F2203/30031 , H03F2203/45222 , H03F2203/45644 , H03F2203/45686 , H03F2203/45702 , H03F2203/45724
摘要： A transimpedance amplifier includes a first inverter having a first input node and a first output node. The first input node is configured to be coupled to an input signal. A second inverter has a second input node and a second output node. The second input node is configured to receive a reference voltage terminal. The first inverter and the second inverter are configured to provide a differential output voltage signal between the first output node and the second output node.
摘要翻译：跨阻放大器包括具有第一输入节点和第一输出节点的第一反相器。第一输入节点被配置为耦合到输入信号。第二反相器具有第二输入节点和第二输出节点。第二输入节点被配置为接收参考电压端子。第一反相器和第二反相器被配置为在第一输出节点和第二输出节点之间提供差分输出电压信号。

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