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1. 发明授权

US07560991B2 Dynamically compensated operational amplifier 有权
标题翻译：动态补偿运算放大器
公开(公告)号：US07560991B2
公开(公告)日：2009-07-14
申请号：US11674150
申请日：2007-02-13
申请人： Chia-Liang Lin , Gerchih Chou , Chao-Cheng Lee
发明人： Chia-Liang Lin , Gerchih Chou , Chao-Cheng Lee
IPC分类号： H03F1/14
CPC分类号： H03F1/086 , H03F1/3211 , H03F3/45183 , H03F2200/153 , H03F2203/45511 , H03F2203/45512 , H03F2203/45514
摘要： An operational amplifier is dynamically compensated depending on the internal state of the operational amplifier. Compensation is fully enabled only when the internal state indicates a risk of instability. When the internal state of the operational amplifier indicates there is no risk of instability, the compensation is totally or partially turned off.
摘要翻译：运算放大器根据运算放大器的内部状态进行动态补偿。仅当内部状态表示不稳定的风险时，补偿才能完全启用。当运算放大器的内部状态表明不存在不稳定的风险时，补偿完全或部分关闭。

2. 发明申请

US20070194850A1 DYNAMICALLY COMPENSATED OPERATIONAL AMPLIFIER 有权
标题翻译：动态补偿运算放大器
公开(公告)号：US20070194850A1
公开(公告)日：2007-08-23
申请号：US11674150
申请日：2007-02-13
申请人： Chia-Liang Lin , GERCHIH CHOU , Chao-Cheng Lee
发明人： Chia-Liang Lin , GERCHIH CHOU , Chao-Cheng Lee
IPC分类号： H03F3/45 , H03F1/14
CPC分类号： H03F1/086 , H03F1/3211 , H03F3/45183 , H03F2200/153 , H03F2203/45511 , H03F2203/45512 , H03F2203/45514
摘要： An operational amplifier is dynamically compensated depending on the internal state of the operational amplifier. Compensation is fully enabled only when the internal state indicates a risk of instability. When the internal state of the operational amplifier indicates there is no risk of instability, the compensation is totally or partially turned off.
摘要翻译：运算放大器根据运算放大器的内部状态进行动态补偿。仅当内部状态表示不稳定的风险时，补偿才能完全启用。当运算放大器的内部状态表明不存在不稳定的风险时，补偿完全或部分关闭。

3. 发明授权

US08410834B2 All digital serial link receiver with low jitter clock regeneration and method thereof 有权
标题翻译：具有低抖动时钟再生的所有数字串行接收器及其方法
公开(公告)号：US08410834B2
公开(公告)日：2013-04-02
申请号：US13044677
申请日：2011-03-10
申请人： Chia-Liang Lin , Gerchih Chou , Pei-Si Wu
发明人： Chia-Liang Lin , Gerchih Chou , Pei-Si Wu
IPC分类号： H03L7/00
CPC分类号： H04L7/0079 , H04L7/033 , H04L7/0337
摘要： An apparatus and method for clock regeneration with low jitter. The method includes the following steps: (a) using a phase lock loop to generate a first clock that is phase locked to a reference clock; (b) using a binary phase detector for generating a phase error signal by detecting a timing difference between the input signal and a second clock; (c) filtering the phase error signal to generate a first control word and a second control word; (d) performing a phase rotation on the first clock by an amount controlled by the first control word to generate the second clock; (e) filtering the second control word to generate a third control word; (f) sampling the third control word to generate a fourth control word using a third clock; and (g) performing a phase rotation on the first clock by an amount controlled by the fourth control word to generate the third clock. Comparable features for performing these steps are provided in the apparatus.
摘要翻译：一种具有低抖动时钟再生的装置和方法。该方法包括以下步骤：（a）使用锁相环产生锁相到参考时钟的第一时钟; （b）使用二进制相位检测器，通过检测输入信号和第二时钟之间的定时差产生相位误差信号; （c）对相位误差信号进行滤波以产生第一控制字和第二控制字; （d）在所述第一时钟上执行由所述第一控制字控制的量的相位旋转以产生所述第二时钟; （e）过滤所述第二控制字以产生第三控制字; （f）使用第三时钟对第三控制字进行采样以产生第四控制字; 以及（g）在所述第一时钟上执行由所述第四控制字控制的量的相位旋转以产生所述第三时钟。在该装置中提供了用于执行这些步骤的相当特征。

4. 发明授权

US07924113B2 Integrated front-end passive equalizer and method thereof 有权
标题翻译：集成前端无源均衡器及其方法
公开(公告)号：US07924113B2
公开(公告)日：2011-04-12
申请号：US12349740
申请日：2009-01-07
申请人： Gerchih Chou , Chia-Liang Lin
发明人： Gerchih Chou , Chia-Liang Lin
IPC分类号： H03H7/38 , H04B3/14
CPC分类号： H04B3/14 , H01L23/64 , H01L2224/05554 , H01L2224/48091 , H01L2224/48227 , H01L2224/49175 , H01L2924/30107 , H01L2924/3011 , H01L2924/30111 , H01L2924/00014 , H01L2924/00
摘要： A passive equalizer circuit incorporated at a front-end of an integrated receiver circuit uses passive components that are distributed between inside and outside of an integrated circuit package. The passive equalizer circuit has off-chip components that are placed on a printed circuit board and on-chip components that are fabricated on a common integrated circuit die as a receiver chip. The on-chip components include one or more variable resistors for adjusting a degree of equalization. The off-chip components include one or more resistors for fine tuning input impedance matching of the integrated receiver circuit.
摘要翻译：集成在集成接收器电路的前端的无源均衡器电路使用分布在集成电路封装的内部和外部的无源部件。无源均衡器电路具有放置在印刷电路板上的片外部件和在作为接收器芯片的公共集成电路管芯上制造的片上部件。片上组件包括用于调节均衡程度的一个或多个可变电阻器。片外部件包括一个或多个用于微调集成接收器电路的输入阻抗匹配的电阻器。

5. 发明授权

US07450041B2 Error cancelling comparator based switch capacitor circuit and method thereof 有权
标题翻译：错误消除基于比较器的开关电容器电路及其方法
公开(公告)号：US07450041B2
公开(公告)日：2008-11-11
申请号：US11277939
申请日：2006-03-29
申请人： Chia-Liang Lin , Gerchih Chou
发明人： Chia-Liang Lin , Gerchih Chou
IPC分类号： H03M1/06
CPC分类号： H03F3/005 , G11C27/026
摘要： An error canceling comparator based switch capacitor (CBSC) circuit cyclically works through multiple phases including a sampling phase and a transfer phase. During the sampling phase, an input voltage and also an error due to circuit non-idealities are sampled. During the transfer phase, the sampled input voltage is amplified by a fixed ratio and transferred to an output load, while the error is cancelled by reversing the polarity of connection for an internal capacitor within the CBSC circuit.
摘要翻译：基于误差消除比较器的开关电容器（CBSC）电路通过多个相位循环工作，包括采样相位和转移相位。在采样阶段，采样输入电压以及电路非理想的误差。在传送阶段，采样输入电压以固定比率放大并转移到输出负载，而通过反转CBSC电路内部电容器的连接极性来消除误差。

6. 发明授权

US07388407B2 Variable delay clock synthesizer 有权
标题翻译：可变延迟时钟合成器
公开(公告)号：US07388407B2
公开(公告)日：2008-06-17
申请号：US11860108
申请日：2007-09-24
申请人： Chia-Liang Lin , Gerchih Chou
发明人： Chia-Liang Lin , Gerchih Chou
IPC分类号： H03B21/50 , H03L7/00
CPC分类号： H03L7/0812 , H03L7/0896
摘要： In an embodiment, a fine resolution of variable clock delay is implemented using a variable DC offset having fine resolution. The proportional ratio between the DC offset and the phase delay/advance of the clock is calibrated in a closed-loop manner. In another embodiment, in a calibration circuit, an adaptive positive DC offset is added to the output of a delay buffer to advance the phase of the clock output, which also has a phase delay from the delay buffer. The DC offset is adjusted in a closed-loop manner to make the phase advance, due to the DC offset, compensate for the phase delay, due to the delay buffer. Once the phase relationship of the DC offset to the clock phase advance is calibrated, the DC offset can be scaled and added to the output of another buffer of the same type to achieve a desired phase delay or advance of the clock signal.
摘要翻译：在一个实施例中，使用具有精细分辨率的可变DC偏移来实现可变时钟延迟的精细分辨率。 DC偏移和时钟的相位延迟/提前之间的比例比例以闭环方式校准。在另一个实施例中，在校准电路中，自适应正DC偏移被加到延迟缓冲器的输出端，以推进时钟输出的相位，该时钟输出也具有来自延迟缓冲器的相位延迟。由于延迟缓冲，由于DC偏移补偿相位延迟，DC偏移以闭环方式进行调整，使相位提前。一旦DC偏移到时钟相位超前的相位关系被校准，则可以将DC偏移量化并相加到相同类型的另一个缓冲器的输出，以实现期望的相位延迟或时钟信号的提前。

7. 发明申请

US20070247201A1 Delay lock clock synthesizer and method thereof 有权
标题翻译：延迟锁定时钟合成器及其方法
公开(公告)号：US20070247201A1
公开(公告)日：2007-10-25
申请号：US11517414
申请日：2006-09-08
申请人： Chia-Liang Lin , Gerchih Chou
发明人： Chia-Liang Lin , Gerchih Chou
IPC分类号： H03L7/06
CPC分类号： H03L7/07 , H03L7/0812 , H03L7/0893 , H03L7/093
摘要： A delay lock clock synthesizer comprises: an adjustable delay circuit for receiving an input clock and for generating an output clock having a phase offset controlled by a control signal; a phase detector for detecting a phase difference between the input clock and the output clock and for generating a phase error signal representing the phase difference; a summing circuit for summing the phase error signal and a phase offset signal into a modified phase error signal; and a filter for filtering the modified phase error signal to generate the control signal to control the adjustable delay circuit.
摘要翻译：延迟锁定时钟合成器包括：可调延迟电路，用于接收输入时钟并产生具有由控制信号控制的相位偏移的输出时钟; 相位检测器，用于检测输入时钟和输出时钟之间的相位差，并产生表示相位差的相位误差信号; 求和电路，用于将相位误差信号和相位偏移信号相加到修正的相位误差信号中; 以及用于对修改的相位误差信号进行滤波以产生控制信号以控制可调延迟电路的滤波器。

8. 发明授权

US07969202B2 Fractional-N frequency synthesizer 有权
标题翻译：分数N频率合成器
公开(公告)号：US07969202B2
公开(公告)日：2011-06-28
申请号：US12353846
申请日：2009-01-14
申请人： Chia-Liang Lin , Gerchih Chou
发明人： Chia-Liang Lin , Gerchih Chou
IPC分类号： G01R25/00 , H03D13/00
CPC分类号： H03L7/1976 , H03L7/0891 , H03L7/0898
摘要： A circuit, with applications to phase-locked loops and frequency synthesis, where a divider circuit shuffles between dividing the output of a voltage-controlled oscillator by N or N+1, where N is an integer, and where a phase frequency detector provides three logic signals to a charge pump so that one of three values of current may be sourced to a loop filter, with the result that the circuit behaves as a conventional phase-locked loop having a fictitious divider circuit that is capable of dividing the output of the voltage-controlled oscillator by a non-integral value.
摘要翻译：一种应用于锁相环和频率合成的电路，其中分压器电路在将压控振荡器的输出除以N或N + 1之间进行洗牌，其中N是整数，并且其中相位频率检测器提供三个逻辑信号到电荷泵，使得电流的三个值中的一个可以被提供给环路滤波器，结果是电路作为常规的锁相环具有虚构的分频器电路，该虚拟分频器电路能够将压控振荡器由非积分值组成。

9. 发明授权

US07629854B2 Switch-capacitor loop filter for phase lock loops 有权
标题翻译：用于锁相环的开关电容环路滤波器
公开(公告)号：US07629854B2
公开(公告)日：2009-12-08
申请号：US11601303
申请日：2006-11-17
申请人： Chia-Liang Lin , Gerchih Chou , Chi-Kung Kuan
发明人： Chia-Liang Lin , Gerchih Chou , Chi-Kung Kuan
IPC分类号： H03L7/085 , H03L7/093 , G06F7/64
CPC分类号： H03L7/0891 , H03L7/093 , H03L7/1976
摘要： A switch-capacitor loop filter is used to generate a control voltage for a voltage-controlled oscillator (VCO) in a phase lock loop (PLL). The switch-capacitor circuit works in a multi-phase manner including at least two non-overlapping phases: a sampling phase and a transfer phase. During the sampling phase, the current representing the phase difference between the reference clock and the feedback clock of the PLL is integrated by a sampling capacitor. During the transfer phase, the charge stored on the sampling capacitor is transferred to a load capacitor. The timing for controlling the switch-capacitor function is derived from the reference clock.
摘要翻译：开关电容环路滤波器用于在锁相环（PLL）中产生压控振荡器（VCO）的控制电压。开关电容器电路以包括至少两个非重叠相位的多相方式工作：采样相位和转移相位。在采样阶段，表示基准时钟与PLL的反馈时钟之间的相位差的电流由采样电容器积分。在转移阶段，存储在采样电容器上的电荷被传送到负载电容器。用于控制开关电容器功能的时序来自参考时钟。

10. 发明授权

US07583117B2 Delay lock clock synthesizer and method thereof 有权
标题翻译：延迟锁定时钟合成器及其方法
公开(公告)号：US07583117B2
公开(公告)日：2009-09-01
申请号：US11517414
申请日：2006-09-08
申请人： Chia-Liang Lin , Gerchih Chou
发明人： Chia-Liang Lin , Gerchih Chou
IPC分类号： H03L7/06
CPC分类号： H03L7/07 , H03L7/0812 , H03L7/0893 , H03L7/093
摘要： A delay lock clock synthesizer comprises: an adjustable delay circuit for receiving an input clock and for generating an output clock having a phase offset controlled by a control signal; a phase detector for detecting a phase difference between the input clock and the output clock and for generating a phase error signal representing the phase difference; a summing circuit for summing the phase error signal and a phase offset signal into a modified phase error signal; and a filter for filtering the modified phase error signal to generate the control signal to control the adjustable delay circuit.
摘要翻译：延迟锁定时钟合成器包括：可调延迟电路，用于接收输入时钟并产生具有由控制信号控制的相位偏移的输出时钟; 相位检测器，用于检测输入时钟和输出时钟之间的相位差，并产生表示相位差的相位误差信号; 求和电路，用于将相位误差信号和相位偏移信号相加到修正的相位误差信号中; 以及用于对修改的相位误差信号进行滤波以产生控制信号以控制可调延迟电路的滤波器。

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