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1. 发明授权

US5706489A Method for a CPU to utilize a parallel instruction execution processing facility for assisting in the processing of the accessed data 失效
标题翻译：用于CPU利用并行指令执行处理设施来协助处理所访问数据的方法
公开(公告)号：US5706489A
公开(公告)日：1998-01-06
申请号：US544496
申请日：1995-10-18
申请人： Chi-Hung Chi , Hatem Mohamed Ghafir , Balakrishna Raghavendra Iyer , Inderpal Singh Narang , Gururaj Seshagiri Rao , Bhaskar Sinha
发明人： Chi-Hung Chi , Hatem Mohamed Ghafir , Balakrishna Raghavendra Iyer , Inderpal Singh Narang , Gururaj Seshagiri Rao , Bhaskar Sinha
IPC分类号： G06F9/38
CPC分类号： G06F9/30076 , G06F9/3863 , G06F9/3877
摘要： A method for obtaining parallel instruction execution (PIE) for frequently used programming operations, such as database record compression or expansion, cryptographic encoding/decoding, page moving, etc., for which a hardware-assist may be provided. These functions can be performed in parallel with CPU processing by a PIE processing facility (PIE-PF). The method is hardware/microcode based and uses software control in supervisory mode. The preferred embodiment is controlled by privileged subsystem software under an operating system, and does not use I/O channel oriented off-load processing. When the CPU is interrupted during an incomplete parallel operation by the PIE-PF, it is checkpointed in main storage in a manner accessible to the subsystem. The subsystem (after completing a current CPU operation, such as a database record predicate evaluation, can check for the completion of the PIE-PF operation by examining an indicator in a control block in shared storage. Furthermore, if the parallel operation has not completed, the CPU can: a) continue the PIE-PF processing in parallel with other processing in the CPU, b) halt the parallel PIE-PF asynchronous operation and have the CPU do the rest of the operation synchronously, or c) resume the parallel operation in the processor or a hardware assist if an interruption caused the PIE-PF parallel operation to be checkpointed.
摘要翻译：用于获得可以提供硬件辅助的频繁使用的编程操作（诸如数据库记录压缩或扩展，加密编码/解码，页面移动等）的并行指令执行（PIE）的方法。这些功能可以与PIE处理设备（PIE-PF）的CPU处理并行执行。该方法是基于硬件/微代码，并以监控模式使用软件控制。优选实施例由操作系统下的特权子系统软件控制，并且不使用I / O通道定向的卸载处理。当CPU在PIE-PF的不完全并行操作期间中断时，它将以子系统可访问的方式在主存储中进行检查。子系统（完成目前的CPU操作，如数据库记录谓词评估）可以通过检查共享存储器中的控制块中的指示符来检查PIE-PF操作的完成情况，此外，如果并行操作未完成 CPU可以：a）与CPU中的其他处理并行执行PIE-PF处理，b）停止并行PIE-PF异步操作，并让CPU同步执行其余操作，或c）恢复并行如果中断导致PIE-PF并行操作被检查点，则处理器中的操作或硬件辅助。

2. 发明授权

US5473764A Multilevel instruction cache 失效
标题翻译：多级指令缓存
公开(公告)号：US5473764A
公开(公告)日：1995-12-05
申请号：US226113
申请日：1994-04-08
申请人： Chi-Hung Chi
发明人： Chi-Hung Chi
IPC分类号： G06F9/30 , G06F9/38 , G06F12/08 , G06F9/26 , G06F12/00
CPC分类号： G06F12/0897 , G06F12/0862 , G06F12/0888 , G06F9/3802 , G06F9/381 , G06F9/3814 , G06F9/383 , G06F2212/6022 , G06F2212/6028
摘要： A cache memory for use between a processing unit and a main memory includes a prefetch buffer, a use buffer, and a head buffer. The prefetched buffer is a FIFO or LRU register which prefetches instructions from contiguous memory locations after the address specified by the program counter. The head buffer is a FIFO or LRU register which is utilized to store instructions from the tops of the program blocks which are accessed from main memory following recent cache misses. The use buffer is a relatively large, inexpensive buffer, preferably a directly mapped buffer, which stores recent hits from the prefetched buffer as well as selected instructions from main memory following cache misses.
摘要翻译：在处理单元和主存储器之间使用的高速缓冲存储器包括预取缓冲器，使用缓冲器和头缓冲器。预取的缓冲器是FIFO或LRU寄存器，它从程序计数器指定的地址之后的连续存储单元中预取指令。头缓冲器是FIFO或LRU寄存器，其用于存储来自程序块的顶部的指令，这些指令是在最近的高速缓存未命中之后从主存储器访问的。使用缓冲器是相对较大且便宜的缓冲器，优选直接映射的缓冲器，其存储来自预取缓冲器的最近命中以及在高速缓存未命中之后来自主存储器的选定指令。

3. 发明授权

US5822757A Computer system with multi-buffer data cache for prefetching data having different temporal and spatial localities 失效
标题翻译：具有多缓冲数据缓存的计算机系统，用于预取具有不同时间和空间地点的数据
公开(公告)号：US5822757A
公开(公告)日：1998-10-13
申请号：US581670
申请日：1995-12-29
申请人： Chi-Hung Chi
发明人： Chi-Hung Chi
IPC分类号： G06F9/38 , G06F12/08 , G06F12/12 , G06F13/00
CPC分类号： G06F12/0848 , G06F12/0862 , G06F9/383 , G06F12/0846 , G06F2212/6028
摘要： A computer system including a multi buffer data cache and method of caching data based on predicted temporal and spatial localities. A processor operates on operands under instruction control, the operands being stored in a main memory. The processor is coupled to the main memory via a data cache for prefetch and storage of operands referenced by the instructions. The data cache comprises an S-buffer for storing operands with strong temporal locality, and a P-buffer for storing operands with strong spatial locality. A control unit connected to the processor, the buffers and the main memory, determines what type of locality is involved in the operand referenced, based on whether the instruction accesses the main memory in a direct or indirect addressing mode as determined by a decoder unit of the processor, and governs operation of the buffer associated with the type of locality determined. Data references may be classified into a plurality of groups, which may include data references to stack data or global variable data, on the basis of predicted statistical associations of localities of the data references. The processor may include a stack pointer register and the computer system may identify requests using the indirect addressing mode based on the stack pointer register.
摘要翻译：一种包括多缓冲数据高速缓存的计算机系统和基于预测的时间和空间地点来缓存数据的方法。处理器对指令控制下的操作数进行操作，操作数存储在主存储器中。处理器经由数据高速缓存用于预取和存储由指令引用的操作数的主存储器。数据高速缓存包括用于存储具有强时间局部性的操作数的S缓冲器，以及用于存储具有强空间局部性的操作数的P缓冲器。连接到处理器，缓冲器和主存储器的控制单元基于指令以直接或间接寻址模式访问主存储器来确定参考的操作数中的哪种类型的位置，由解码器单元确定处理器，并且控制与确定的本地类型相关联的缓冲器的操作。数据引用可以分为多个组，其可以包括基于数据引用的地点的预测统计关联的堆栈数据或全局变量数据的数据引用。处理器可以包括堆栈指针寄存器，并且计算机系统可以使用基于堆栈指针寄存器的间接寻址模式来识别请求。

4. 发明授权

US5784711A Data cache prefetching under control of instruction cache 失效
标题翻译：数据缓存在指令缓存控制下预取
公开(公告)号：US5784711A
公开(公告)日：1998-07-21
申请号：US080438
申请日：1993-06-21
申请人： Chi-Hung Chi
发明人： Chi-Hung Chi
IPC分类号： G06F9/30 , G06F9/38 , G06F12/08 , G06F9/32
CPC分类号： G06F9/3814 , G06F12/0862 , G06F12/0888 , G06F9/30105 , G06F9/381 , G06F9/383 , G06F9/3838 , G06F2212/6022 , G06F2212/6028
摘要： A data prefetching arrangement for use between a computer processor and a main memory. The addresses of data to be prefetched are calculated by decoding instructions which have been prefetched by decoding prefetched instructions, the instructions having been in accordance with an intelligent prefetching scheme. The processor registers have two sections for respective access by the processor and a prefetch controller. The instruction registers may also contain an additional counter field which indicates the number of instruction cycles which must be executed before the register may be reliably utilized for prefetching data.
摘要翻译：一种在计算机处理器和主存储器之间使用的数据预取配置。要预取的数据的地址是通过对通过解码预取指令预取的指令进行解码的，该指令已经符合智能预取方案。处理器寄存器有两个部分用于处理器和预取控制器的相应访问。指令寄存器还可以包含附加计数器字段，其指示在寄存器可以可靠地用于预取数据之前必须执行的指令周期数。

5. 发明授权

US5701435A Instruction cache system for implementing programs having non-sequential instructions and method of implementing same 失效
标题翻译：用于实现具有非顺序指令的程序的指令缓存系统及其实现方法
公开(公告)号：US5701435A
公开(公告)日：1997-12-23
申请号：US63845
申请日：1993-05-19
申请人： Chi-Hung Chi
发明人： Chi-Hung Chi
IPC分类号： G06F9/38 , G06F12/08 , G06F12/12
CPC分类号： G06F9/3808 , G06F12/0862 , G06F9/381 , G06F12/0875 , G06F2212/6028
摘要： A system for increasing the speed and efficiency of instruction execution by a computer processing system. An instruction cache is provided to receive a minor number of stored instructions for execution by the computer processing system. The instructions are prefetched and returned in cache based upon an analysis of instructions which are in the cache pending execution. Target instructions of branch instructions may be prefetched as a result of the analysis of a branch instruction pending in the cache. Other instructions may be retained in cache when they are tagged as being likely to be reused.
摘要翻译：一种用于增加计算机处理系统的指令执行的速度和效率的系统。提供指令高速缓存以接收由计算机处理系统执行的少量存储的指令。这些指令是基于缓存中待处理执行中的指令的分析而被预取并在高速缓存中返回的。分支指令的目标指令可以作为分析高速缓存中待处理的分支指令的结果而被预取。当它们被标记为可能被重用时，其他指令可以保留在高速缓存中。

6. 发明授权

US5303377A Method for compiling computer instructions for increasing instruction cache efficiency 失效
标题翻译：用于编译计算机指令以提高指令高速缓存效率的方法
公开(公告)号：US5303377A
公开(公告)日：1994-04-12
申请号：US500627
申请日：1990-03-27
申请人： Rajiv Gupta , Chi-Hung Chi
发明人： Rajiv Gupta , Chi-Hung Chi
IPC分类号： G06F12/08 , G06F9/45 , G06F12/12 , G06F9/44
CPC分类号： G06F8/4442
摘要： Method for compiling program instructions to reduce instruction cache misses and instruction cache pollution. The program is analyzed for instructions which result in a non-sequential transfer of control in the program. The presence of branch instructions and program loops are identified and analyzed. The instructions are placed in lines, and the lines are placed in a sequence to minimize potential misses.
摘要翻译：用于编译程序指令以减少指令高速缓存未命中和指令高速缓存污染的方法。分析该程序的指令，导致程序中的非顺序传输控制。分支指令和程序循环的存在被识别和分析。指令放置在一行中，并按顺序放置线以最小化潜在的错误。

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