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1. 发明授权

US08546226B2 SONOS non-volatile memory cell and fabricating method thereof 有权
标题翻译： SONOS非易失性存储单元及其制造方法
公开(公告)号：US08546226B2
公开(公告)日：2013-10-01
申请号：US13189632
申请日：2011-07-25
申请人： Chih-Ming Wang , Ping-Chia Shih , Chun-Sung Huang , Chi-Cheng Huang , Hsiang-Chen Lee , Chih-Hung Lin , Yau-Kae Sheu
发明人： Chih-Ming Wang , Ping-Chia Shih , Chun-Sung Huang , Chi-Cheng Huang , Hsiang-Chen Lee , Chih-Hung Lin , Yau-Kae Sheu
IPC分类号： H01L21/336 , H01L29/792
CPC分类号： H01L21/28282 , H01L29/792
摘要： A method for fabricating a silicon-oxide-nitride-oxide-silicon (SONOS) non-volatile memory cell, wherein the method comprises steps as following: a pad oxide layer and a first hard mask layer are sequentially formed on a substrate. The pad oxide layer and the first hard mask layer are then etched through to form an opening exposing a portion of the substrate. Subsequently, an oxide-nitride-oxide (ONO) structure with a size substantially less than or equal to the opening is formed to coincide with the portion of the substrate exposed from the opening.
摘要翻译：一种用于制造氧化硅 - 氧化物 - 氧化物 - 硅（SONOS）非易失性存储单元的方法，其中该方法包括以下步骤：在衬底上依次形成衬垫氧化物层和第一硬掩模层。然后将衬垫氧化物层和第一硬掩模层蚀刻通过以形成露出衬底的一部分的开口。随后，形成具有基本上小于或等于该开口的尺寸的氧化物 - 氧化物 - 氧化物（ONO）结构，以与从该开口露出的该基板的一部分重合。

2. 发明授权

US08546871B2 Non-volatile memory cell and fabricating method thereof 有权
标题翻译：非易失性存储单元及其制造方法
公开(公告)号：US08546871B2
公开(公告)日：2013-10-01
申请号：US13177520
申请日：2011-07-06
申请人： Chi-Cheng Huang , Ping-Chia Shih , Chih-Ming Wang , Chun-Sung Huang , Hsiang-Chen Lee , Chih-Hung Lin , Yau-Kae Sheu
发明人： Chi-Cheng Huang , Ping-Chia Shih , Chih-Ming Wang , Chun-Sung Huang , Hsiang-Chen Lee , Chih-Hung Lin , Yau-Kae Sheu
IPC分类号： H01L29/792
CPC分类号： H01L29/7923 , H01L29/66833
摘要： A non-volatile memory cell includes a substrate, two charge trapping structures, a gate oxide layer, a gate and two doping regions. The charge trapping structures are disposed on the substrate separately. The gate oxide layer is disposed on the substrate between the two charge trapping structures. The gate is disposed on the gate oxide layer and the charge trapping structures, wherein the charge trapping structures protrude from two sides of the gate. The doping regions are disposed in the substrate at two sides of the gate.
摘要翻译：非易失性存储单元包括衬底，两个电荷俘获结构，栅极氧化层，栅极和两个掺杂区域。电荷捕获结构分别设置在基板上。栅极氧化层设置在两个电荷俘获结构之间的衬底上。栅极设置在栅极氧化物层和电荷捕获结构上，其中电荷捕获结构从栅极的两侧突出。掺杂区域设置在栅极两侧的衬底中。

3. 发明申请

US20130009232A1 NON-VOLATILE MEMORY CELL AND FABRICATING METHOD THEREOF 有权
标题翻译：非挥发性记忆细胞及其制备方法
公开(公告)号：US20130009232A1
公开(公告)日：2013-01-10
申请号：US13177520
申请日：2011-07-06
申请人： Chi-Cheng Huang , Ping-Chia Shih , Chih-Ming Wang , Chun-Sung Huang , Hsiang-Chen Lee , Chih-Hung Lin , Yau-Kae Sheu
发明人： Chi-Cheng Huang , Ping-Chia Shih , Chih-Ming Wang , Chun-Sung Huang , Hsiang-Chen Lee , Chih-Hung Lin , Yau-Kae Sheu
IPC分类号： H01L29/792 , H01L21/336
CPC分类号： H01L29/7923 , H01L29/66833
摘要： A non-volatile memory cell includes a substrate, two charge trapping structures, a gate oxide layer, a gate and two doping regions. The charge trapping structures are disposed on the substrate separately. The gate oxide layer is disposed on the substrate between the two charge trapping structures. The gate is disposed on the gate oxide layer and the charge trapping structures, wherein the charge trapping structures protrude from two sides of the gate. The doping regions are disposed in the substrate at two sides of the gate.
摘要翻译：非易失性存储单元包括衬底，两个电荷俘获结构，栅极氧化层，栅极和两个掺杂区域。电荷捕获结构分别设置在基板上。栅极氧化层设置在两个电荷俘获结构之间的衬底上。栅极设置在栅极氧化物层和电荷捕获结构上，其中电荷捕获结构从栅极的两侧突出。掺杂区域设置在栅极两侧的衬底中。

4. 发明授权

US08383480B1 Method for forming semiconductor structure and method for forming memory using the same 有权
标题翻译：用于形成半导体结构的方法和使用其形成存储器的方法
公开(公告)号：US08383480B1
公开(公告)日：2013-02-26
申请号：US13295191
申请日：2011-11-14
申请人： Chih-Ming Wang , Ping-Chia Shih , Chi-Cheng Huang , Hsiang-Chen Lee , Chih-Hung Lin
发明人： Chih-Ming Wang , Ping-Chia Shih , Chi-Cheng Huang , Hsiang-Chen Lee , Chih-Hung Lin
IPC分类号： H01L21/336
CPC分类号： H01L29/4234 , H01L21/28282 , H01L29/66833 , H01L29/792
摘要： A method for forming a semiconductor structure includes following steps. A substrate structure is provided. The substrate structure includes a semiconductor substrate, a first oxide-nitride-oxide (ONO) layer, and a second ONO layer. The semiconductor substrate has first and second surfaces opposite to each other. The first ONO layer includes a first oxide layer, a first nitride layer and a second oxide layer formed on the first surface in sequence. The second ONO layer includes a third oxide layer, a second nitride layer and a fourth oxide layer formed on the second surface in sequence. A nitride mask layer is formed on the first ONO layer. The fourth oxide layer is removed. The second nitride layer and the nitride mask layer are removed. The second oxide layer and the third oxide layer are removed. A fifth oxide layer is formed on the first nitride layer.
摘要翻译：一种形成半导体结构的方法包括以下步骤。提供了基板结构。衬底结构包括半导体衬底，第一氧化物 - 氧化物 - 氧化物（ONO）层和第二ONO层。半导体衬底具有彼此相对的第一和第二表面。第一ONO层包括顺序地形成在第一表面上的第一氧化物层，第一氮化物层和第二氧化物层。第二ONO层包括依次形成在第二表面上的第三氧化物层，第二氮化物层和第四氧化物层。在第一ONO层上形成氮化物掩模层。去除第四氧化物层。去除第二氮化物层和氮化物掩模层。去除第二氧化物层和第三氧化物层。在第一氮化物层上形成第五氧化物层。

5. 发明申请

US20130234252A1 INTEGRATED CIRCUIT AND METHOD FOR FABRICATING THE SAME 审中-公开
标题翻译：集成电路及其制造方法
公开(公告)号：US20130234252A1
公开(公告)日：2013-09-12
申请号：US13412714
申请日：2012-03-06
申请人： Hsiang-Chen LEE , Ping-Chia Shih , Ke-Chi Chen , Chih-Ming Wang , Chi-Cheng Huang
发明人： Hsiang-Chen LEE , Ping-Chia Shih , Ke-Chi Chen , Chih-Ming Wang , Chi-Cheng Huang
IPC分类号： H01L27/088 , H01L21/336
CPC分类号： H01L21/82345 , H01L21/823807 , H01L21/823835 , H01L21/823842 , H01L21/823857
摘要： An integrated circuit includes a substrate, a first semiconductor device, a second semiconductor device and an interlayer dielectric layer. At least one isolation structure has been formed in the he substrate so as to separate the substrate into a first active region and a second active region. The first semiconductor device disposed on the first active region of the substrate includes a first gate insulating layer and a poly-silicon gate stacked on the substrate sequentially. The second semiconductor device disposed on the second active region of the substrate includes a second gate insulating layer and a metal gate stacked on the substrate sequentially. The material of the second gate insulating layer is different from that of the first gate insulating layer. The thickness of the metal gate is greater than that of the poly-silicon gate. The interlayer dielectric layer is disposed on the substrate and covering the first semiconductor device.
摘要翻译：集成电路包括衬底，第一半导体器件，第二半导体器件和层间电介质层。在衬底中形成至少一个隔离结构，以将衬底分离成第一有源区和第二有源区。设置在基板的第一有源区上的第一半导体器件包括依次层叠在基板上的第一栅极绝缘层和多晶硅栅极。设置在基板的第二有源区上的第二半导体器件包括依次层叠在基板上的第二栅极绝缘层和金属栅极。第二栅极绝缘层的材料与第一栅极绝缘层的材料不同。金属栅极的厚度大于多晶硅栅极的厚度。层间介质层设置在基板上并覆盖第一半导体器件。

6. 发明授权

US08629025B2 Semiconductor device and method for fabricating semiconductor device 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08629025B2
公开(公告)日：2014-01-14
申请号：US13403591
申请日：2012-02-23
申请人： Ko-Chi Chen , Ping-Chia Shih , Chih-Ming Wang , Chi-Cheng Huang , Hsiang-Chen Lee
发明人： Ko-Chi Chen , Ping-Chia Shih , Chih-Ming Wang , Chi-Cheng Huang , Hsiang-Chen Lee
IPC分类号： H01L29/792 , H01L21/336
CPC分类号： H01L29/792 , H01L21/28282 , H01L27/11573 , H01L29/665 , H01L29/66833 , H01L29/7833
摘要： A method for fabricating a semiconductor device is described. A stacked gate dielectric is formed over a substrate, including a first dielectric layer, a second dielectric layer and a third dielectric layer from bottom to top. A conductive layer is formed on the stacked gate dielectric and then patterned to form a gate conductor. The exposed portion of the third and the second dielectric layers are removed with a selective wet cleaning step. S/D extension regions are formed in the substrate with the gate conductor as a mask. A first spacer is formed on the sidewall of the gate conductor and a portion of the first dielectric layer exposed by the first spacer is removed. S/D regions are formed in the substrate at both sides of the first spacer. A metal silicide layer is formed on the S/D regions.
摘要翻译：对半导体装置的制造方法进行说明。堆叠的栅极电介质形成在衬底上，包括从底部到顶部的第一介电层，第二电介质层和第三电介质层。在堆叠的栅极电介质上形成导电层，然后将其图案化以形成栅极导体。通过选择性湿式清洗步骤除去第三和第二介电层的暴露部分。在栅极导体作为掩模的基板中形成S / D延伸区域。在栅极导体的侧壁上形成第一间隔物，并且去除由第一间隔物露出的第一电介质层的一部分。在第一间隔物的两侧的基板中形成S / D区域。在S / D区域上形成金属硅化物层。

7. 发明申请

US20130221424A1 SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING SEMICONDUCTOR DEVICE 有权
标题翻译：用于制造半导体器件的半导体器件和方法
公开(公告)号：US20130221424A1
公开(公告)日：2013-08-29
申请号：US13403591
申请日：2012-02-23
申请人： Ko-Chi Chen , Ping-Chia Shih , Chih-Ming Wang , Chi-Cheng Huang , Hsiang-Chen Lee
发明人： Ko-Chi Chen , Ping-Chia Shih , Chih-Ming Wang , Chi-Cheng Huang , Hsiang-Chen Lee
IPC分类号： H01L29/792 , H01L21/336
CPC分类号： H01L29/792 , H01L21/28282 , H01L27/11573 , H01L29/665 , H01L29/66833 , H01L29/7833
摘要： A method for fabricating a semiconductor device is described. A stacked gate dielectric is formed over a substrate, including a first dielectric layer, a second dielectric layer and a third dielectric layer from bottom to top. A conductive layer is formed on the stacked gate dielectric and then patterned to form a gate conductor. The exposed portion of the third and the second dielectric layers are removed with a selective wet cleaning step. S/D extension regions are formed in the substrate with the gate conductor as a mask. A first spacer is formed on the sidewall of the gate conductor and a portion of the first dielectric layer exposed by the first spacer is removed. S/D regions are formed in the substrate at both sides of the first spacer. A metal silicide layer is formed on the S/D regions.
摘要翻译：对半导体装置的制造方法进行说明。堆叠的栅极电介质形成在衬底上，包括从底部到顶部的第一介电层，第二电介质层和第三电介质层。在堆叠的栅极电介质上形成导电层，然后将其图案化以形成栅极导体。通过选择性湿式清洗步骤除去第三和第二介电层的暴露部分。在栅极导体作为掩模的基板中形成S / D延伸区域。在栅极导体的侧壁上形成第一间隔物，并且去除由第一间隔物露出的第一电介质层的一部分。在第一间隔物的两侧的基板中形成S / D区域。在S / D区域上形成金属硅化物层。

8. 发明申请

US20100200905A1 NAND MEMORY CELLS AND MANUFACTURING METHOD THEREOF 有权
标题翻译： NAND存储器及其制造方法
公开(公告)号：US20100200905A1
公开(公告)日：2010-08-12
申请号：US12368223
申请日：2009-02-09
申请人： Chun-Sung Huang , Ping-Chia Shih , Chiao-Lin Yang , Chi-Cheng Huang
发明人： Chun-Sung Huang , Ping-Chia Shih , Chiao-Lin Yang , Chi-Cheng Huang
IPC分类号： H01L29/51 , H01L21/336 , H01L21/302
CPC分类号： H01L27/11568 , H01L27/11521 , H01L29/66825 , H01L29/66833
摘要： A method for manufacturing NAND memory cells includes providing a substrate having a first doped region formed therein; sequentially forming a first dielectric layer, a storage layer and a patterned hard mask on the substrate; forming a STI defining a plurality of recesses in the substrate through the patterned hard mask; sequentially forming a second dielectric layer and a first conductive layer filling the recesses on the substrate; and performing a planarization process to remove a portion of the first conductive layer and the second dielectric layer to form a plurality of self-aligned islanding gate structures.
摘要翻译：一种用于制造NAND存储器单元的方法包括提供其中形成有第一掺杂区的衬底; 在基板上依次形成第一介电层，存储层和图案化的硬掩模; 通过图案化的硬掩模形成在衬底中限定多个凹槽的STI; 顺序地形成第二电介质层和填充衬底上的凹部的第一导电层; 以及执行平坦化处理以去除所述第一导电层和所述第二介电层的一部分以形成多个自对准岛状栅极结构。

9. 发明授权

US07973353B2 NAND memory cells 有权
标题翻译： NAND存储器单元
公开(公告)号：US07973353B2
公开(公告)日：2011-07-05
申请号：US12368223
申请日：2009-02-09
申请人： Chun-Sung Huang , Ping-Chia Shih , Chiao-Lin Yang , Chi-Cheng Huang
发明人： Chun-Sung Huang , Ping-Chia Shih , Chiao-Lin Yang , Chi-Cheng Huang
IPC分类号： H01L29/76 , H01L29/792 , H01L29/00
CPC分类号： H01L27/11568 , H01L27/11521 , H01L29/66825 , H01L29/66833
摘要： A method for manufacturing NAND memory cells includes providing a substrate having a first doped region formed therein; sequentially forming a first dielectric layer, a storage layer and a patterned hard mask on the substrate; forming a STI defining a plurality of recesses in the substrate through the patterned hard mask; sequentially forming a second dielectric layer and a first conductive layer filling the recesses on the substrate; and performing a planarization process to remove a portion of the first conductive layer and the second dielectric layer to form a plurality of self-aligned islanding gate structures.
摘要翻译：一种用于制造NAND存储器单元的方法包括提供其中形成有第一掺杂区的衬底; 在基板上依次形成第一介电层，存储层和图案化的硬掩模; 通过图案化的硬掩模形成在衬底中限定多个凹槽的STI; 顺序地形成第二电介质层和填充衬底上的凹部的第一导电层; 以及执行平坦化处理以去除所述第一导电层和所述第二介电层的一部分以形成多个自对准岛状栅极结构。

10. 发明授权

US08222112B2 Method for manufacturing NAND memory cells 有权
标题翻译：制造NAND存储器单元的方法
公开(公告)号：US08222112B2
公开(公告)日：2012-07-17
申请号：US13114045
申请日：2011-05-24
申请人： Chun-Sung Huang , Ping-Chia Shih , Chiao-Lin Yang , Chi-Cheng Huang
发明人： Chun-Sung Huang , Ping-Chia Shih , Chiao-Lin Yang , Chi-Cheng Huang
IPC分类号： H01L29/792 , H01L21/336
CPC分类号： H01L27/11568 , H01L27/11521 , H01L29/66825 , H01L29/66833
摘要： A method for manufacturing NAND memory cells includes providing a substrate having a first doped region formed therein; forming a first dielectric layer, a storage layer and a patterned hard mask on the substrate; forming a STI in the substrate through the patterned hard mask and removing the patterned hard mask to define a plurality of recesses; forming a second dielectric layer and a first conductive layer filling the recesses on the substrate; and performing a planarization process to remove a portion of the first conductive layer and the second dielectric layer to form a plurality of self-aligned islanding gate structures.
摘要翻译：一种用于制造NAND存储器单元的方法包括提供其中形成有第一掺杂区的衬底; 在基板上形成第一电介质层，存储层和图案化的硬掩模; 通过图案化的硬掩模在衬底中形成STI，并去除图案化的硬掩模以限定多个凹槽; 形成第二电介质层和填充所述基板上的所述凹部的第一导电层; 以及执行平坦化处理以去除所述第一导电层和所述第二介电层的一部分以形成多个自对准岛状栅极结构。

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