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1. 发明授权

US06773338B2 Polishing head and chemical mechanical polishing apparatus including the same 有权
标题翻译：抛光头和化学机械抛光装置包括它
公开(公告)号：US06773338B2
公开(公告)日：2004-08-10
申请号：US10357471
申请日：2003-02-04
申请人： Cheol-Ju Yun , Young-Min Kim
发明人： Cheol-Ju Yun , Young-Min Kim
IPC分类号： B24B100
CPC分类号： B24B37/32 , B24B49/04
摘要： A polishing head and a chemical mechanical polishing apparatus having the polishing head including a plate having vacuum holes for transferring vacuum pumping force; a porous film having holes corresponding to the vacuum holes and attached to a lower surface of the plate; a retainer ring attached to the lower surface of the plate at an edge portion thereof and having a sloped surface; a clamp ring attached to the lower surface of the plate adjacent the retainer ring for clamping the retainer ring; an adjusting ring having a sloped surface parallel and in contact with the sloped surface of the retainer ring, the adjusting ring being installed between the retainer ring and the plate; and a diameter adjusting device for adjusting a diameter of the adjusting ring by moving the adjusting ring along the sloped surface of the retainer ring, thereby adjusting a height of the retainer ring.
摘要翻译：一种抛光头和化学机械抛光装置，其具有包括具有用于传递真空抽吸力的真空孔的板的抛光头; 多孔膜，其具有与所述真空孔对应的孔，并且附着到所述板的下表面; 保持环在其边缘部分处附接到板的下表面并具有倾斜表面; 夹紧环，其附接到邻近保持环的板的下表面，用于夹持保持环; 调节环，其具有平行于所述保持环的倾斜表面的倾斜表面，所述调节环安装在所述保持环和所述板之间; 以及直径调节装置，用于通过沿着保持环的倾斜表面移动调节环来调节调节环的直径，从而调节保持环的高度。

2. 发明授权

US07307305B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07307305B2
公开(公告)日：2007-12-11
申请号：US11143197
申请日：2005-06-01
申请人： Jae-Goo Lee , Cheol-Ju Yun
发明人： Jae-Goo Lee , Cheol-Ju Yun
IPC分类号： H01L27/108
CPC分类号： H01L27/10888 , H01L27/0207 , H01L27/10814 , H01L27/10855 , H01L27/10885
摘要： Bit lines having first conductive patterns and bit line mask patterns are formed on a first insulating layer between capacitor contact regions of a substrate. An oxide second insulating layer is formed on the bit lines and contact patterns are formed to open storage node contact hole regions corresponding to portions of the second insulating layer. First spacers are formed on sidewalls of the etched portions. The second and first insulating layers are etched to form storage node contact holes exposing the capacitor contact regions. Simultaneously, second spacers of the second insulating layer are formed beneath the first spacers. A second conductive layer fills the storage node contact holes to form storage node contact pads. A loss of the bit line mask pattern decreases due to the reduced thickness of the bit line mask pattern and a bit line loading capacitance decreases due to the second spacers.
摘要翻译：具有第一导电图案和位线掩模图案的位线形成在衬底的电容器接触区域之间的第一绝缘层上。在位线上形成氧化物第二绝缘层，并且形成接触图案以打开与第二绝缘层的部分相对应的存储节点接触孔区域。在蚀刻部分的侧壁上形成第一间隔物。蚀刻第二和第一绝缘层以形成暴露电容器接触区域的存储节点接触孔。同时，第二绝缘层的第二间隔件形成在第一间隔件下面。第二导电层填充存储节点接触孔以形成存储节点接触焊盘。由于位线掩模图案的厚度减小，位线掩模图案的损失减小，并且位线负载电容由于第二间隔件而减小。

3. 发明申请

US20050272250A1 Method of forming self-aligned contact and method of manufacturing semiconductor memory device by using the same 审中-公开
标题翻译：形成自对准接触的方法和使用该半导体存储器件的半导体存储器件的制造方法
公开(公告)号：US20050272250A1
公开(公告)日：2005-12-08
申请号：US11147953
申请日：2005-06-07
申请人： Cheol-Ju Yun , Tae-Young Chung , In-Ho Nam
发明人： Cheol-Ju Yun , Tae-Young Chung , In-Ho Nam
IPC分类号： H01L21/28 , H01L21/44 , H01L21/4763 , H01L21/48 , H01L21/50 , H01L21/60 , H01L21/8242 , H01L23/522 , H01L27/108
CPC分类号： H01L27/10885 , H01L21/486 , H01L21/76897 , H01L23/5222 , H01L23/5226 , H01L27/10814 , H01L27/10855 , H01L2924/0002 , H01L2924/00
摘要： In an embodiment a method of forming self-aligned contacts in a semiconductor memory device includes: forming conductive stacks of conductive layers on a semiconductor substrate; forming insulating spacer layers on sidewalls of the conductive stacks; forming an insulating layer; forming a capping insulating layer covering portions of the insulating layer; and forming conductive pads that fill the contact holes to contact the semiconductor substrate. The capping insulating layer has a function of a buffer, so an etched amount of mask layers insulating the conductive layers is minimized, and a probability of a short circuit between capacitor electrodes and the conductive stacks is greatly reduced.
摘要翻译：在一个实施例中，在半导体存储器件中形成自对准触点的方法包括：在半导体衬底上形成导电层的导电层; 在导电叠层的侧壁上形成绝缘间隔层; 形成绝缘层; 形成覆盖所述绝缘层的部分的覆盖绝缘层; 以及形成填充接触孔以接触半导体衬底的导电焊盘。封盖绝缘层具有缓冲器的功能，因此绝缘导电层的掩模层的蚀刻量最小化，电容器电极和导电叠层之间的短路的可能性大大降低。

4. 发明授权

US06967150B2 Method of forming self-aligned contact in fabricating semiconductor device 有权
标题翻译：在制造半导体器件中形成自对准接触的方法
公开(公告)号：US06967150B2
公开(公告)日：2005-11-22
申请号：US10938154
申请日：2004-09-10
申请人： Cheol-Ju Yun , Tae-Young Chung
发明人： Cheol-Ju Yun , Tae-Young Chung
IPC分类号： H01L21/28 , H01L21/3205 , H01L21/4763 , H01L21/60 , H01L21/768 , H01L21/8242
CPC分类号： H01L27/10885 , H01L21/76804 , H01L21/76831 , H01L21/76897 , H01L27/10855
摘要： According to some embodiments of the invention, a method of forming a self-aligned contact of a semiconductor device includes forming a plurality of conductive lines that are spaced apart from each other and pass over a plurality of conductive regions. An insulating layer is formed over and between the conductive lines. A plurality of contact holes are then formed to selectively expose the conductive regions by selectively removing the insulating layer without exposing the conductive lines. The contact holes are extended using an isotropic etching until the conductive lines begin to be exposed. Thereafter, contacts are formed in the contact holes such that the contacts are coupled to the conductive regions.
摘要翻译：根据本发明的一些实施例，形成半导体器件的自对准接触的方法包括形成彼此间隔开并跨越多个导电区域的多条导线。在导线之间和之间形成绝缘层。然后形成多个接触孔，以通过选择性地去除绝缘层而不暴露导电线来选择性地暴露导电区域。使用各向同性蚀刻使接触孔延伸，直到导线开始暴露。此后，在接触孔中形成触点，使得触点耦合到导电区域。

5. 发明申请

US20050218439A1 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20050218439A1
公开(公告)日：2005-10-06
申请号：US11143197
申请日：2005-06-01
申请人： Jae-Goo Lee , Cheol-Ju Yun
发明人： Jae-Goo Lee , Cheol-Ju Yun
IPC分类号： H01L21/768 , H01L21/4763 , H01L21/8242 , H01L27/108 , H01L29/76
CPC分类号： H01L27/10888 , H01L27/0207 , H01L27/10814 , H01L27/10855 , H01L27/10885
摘要： Bit lines having first conductive patterns and bit line mask patterns are formed on a first insulating layer between capacitor contact regions of a substrate. An oxide second insulating layer is formed on the bit lines and contact patterns are formed to open storage node contact hole regions corresponding to portions of the second insulating layer. First spacers are formed on sidewalls of the etched portions. The second and first insulating layers are etched to form storage node contact holes exposing the capacitor contact regions. Simultaneously, second spacers of the second insulating layer are formed beneath the first spacers. A second conductive layer fills the storage node contact holes to form storage node contact pads. A loss of the bit line mask pattern decreases due to the reduced thickness of the bit line mask pattern and a bit line loading capacitance decreases due to the second spacers.
摘要翻译：具有第一导电图案和位线掩模图案的位线形成在衬底的电容器接触区域之间的第一绝缘层上。在位线上形成氧化物第二绝缘层，并且形成接触图案以打开与第二绝缘层的部分相对应的存储节点接触孔区域。在蚀刻部分的侧壁上形成第一间隔物。蚀刻第二和第一绝缘层以形成暴露电容器接触区域的存储节点接触孔。同时，第二绝缘层的第二间隔件形成在第一间隔件下面。第二导电层填充存储节点接触孔以形成存储节点接触焊盘。由于位线掩模图案的厚度减小，位线掩模图案的损失减小，并且位线负载电容由于第二间隔件而减小。

6. 发明授权

US07557410B2 Dynamic random access memory device 有权
标题翻译：动态随机存取存储器
公开(公告)号：US07557410B2
公开(公告)日：2009-07-07
申请号：US11769260
申请日：2007-06-27
申请人： Jin-Woo Lee , Cheol-Ju Yun , Hyeoung-Won Seo
发明人： Jin-Woo Lee , Cheol-Ju Yun , Hyeoung-Won Seo
IPC分类号： H01L29/76 , H01L29/94 , H01L31/00
CPC分类号： H01L27/10814 , H01L27/10823 , H01L27/10852 , H01L27/10873 , H01L27/10876 , H01L27/10885 , H01L27/10888 , H01L28/91 , H01L29/6659
摘要： A semiconductor device comprises a plurality of gate structures formed on a substrate, a gate spacer formed on a sidewall of the gate structures, a semiconductor pattern formed on the substrate between the gate structures, a first impurity region and a second impurity region formed in the semiconductor pattern and at surface portions of the substrate, respectively, wherein the first and second impurity regions include a first conductive type impurity, and a channel doping region surrounding the first impurity region, wherein the channel doping region includes a second conductive type impurity.
摘要翻译：半导体器件包括形成在衬底上的多个栅极结构，形成在栅极结构的侧壁上的栅极间隔物，形成在栅极结构之间的衬底上的半导体图案，形成在栅极结构中的第一杂质区域和第二杂质区域半导体图案和衬底的表面部分，其中第一和第二杂质区域包括第一导电类型杂质和围绕第一杂质区的沟道掺杂区域，其中沟道掺杂区域包括第二导电类型杂质。

7. 发明授权

US07482222B2 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07482222B2
公开(公告)日：2009-01-27
申请号：US11769276
申请日：2007-06-27
申请人： Jin-Woo Lee , Cheol-Ju Yun , Hyeoung-Won Seo
发明人： Jin-Woo Lee , Cheol-Ju Yun , Hyeoung-Won Seo
IPC分类号： H01L21/8242
CPC分类号： H01L27/10814 , H01L27/10823 , H01L27/10852 , H01L27/10873 , H01L27/10876 , H01L27/10885 , H01L27/10888 , H01L28/91 , H01L29/6659
摘要： A semiconductor device comprises a plurality of gate structures formed on a substrate, a gate spacer formed on a sidewall of the gate structures, a semiconductor pattern formed on the substrate between the gate structures, a first impurity region and a second impurity region formed in the semiconductor pattern and at surface portions of the substrate, respectively, wherein the first and second impurity regions include a first conductive type impurity, and a channel doping region surrounding the first impurity region, wherein the channel doping region includes a second conductive type impurity.
摘要翻译：半导体器件包括形成在衬底上的多个栅极结构，形成在栅极结构的侧壁上的栅极间隔物，形成在栅极结构之间的衬底上的半导体图案，形成在栅极结构中的第一杂质区域和第二杂质区域半导体图案和衬底的表面部分，其中第一和第二杂质区域包括第一导电类型杂质和围绕第一杂质区的沟道掺杂区域，其中沟道掺杂区域包括第二导电类型杂质。

8. 发明授权

US07691719B2 Semiconductor device having storage nodes and its method of fabrication 失效
标题翻译：具有存储节点的半导体器件及其制造方法
公开(公告)号：US07691719B2
公开(公告)日：2010-04-06
申请号：US11457726
申请日：2006-07-14
申请人： Cheol-Ju Yun , Kang-Yoon Lee , In-Ho Nam
发明人： Cheol-Ju Yun , Kang-Yoon Lee , In-Ho Nam
IPC分类号： H01L21/20 , H01L21/8242
CPC分类号： H01L21/76885 , H01L21/76834 , H01L27/10855
摘要： Embodiments of a semiconductor device having storage nodes include an interlayer insulating layer disposed on a semiconductor substrate; a conductive pad disposed in the interlayer insulating layer to contact with a predetermined portion of the substrate, an upper portion of the conductive pad protruding above the interlayer insulating layer; an etch stop layer disposed on the conductive pad and the interlayer insulating layer; and storage nodes penetrating the etch stop layer and disposed on the conductive pad. A penetration path of wet etchant is completely blocked during the wet etch process that removes the mold oxide layer. Therefore, inadvertent etching of the insulating layer due to penetration of wet etchant is prevented, resulting in a stronger, more stable, storage node structure.
摘要翻译：具有存储节点的半导体器件的实施例包括设置在半导体衬底上的层间绝缘层; 布置在所述层间绝缘层中以与所述基板的预定部分接触的导电焊盘，所述导电焊盘的上部突出于所述层间绝缘层的上方; 设置在所述导电焊盘和所述层间绝缘层上的蚀刻停止层; 并且存储节点穿透蚀刻停止层并且设置在导电焊盘上。在湿法蚀刻工艺期间，湿蚀刻剂的穿透路径被完全阻挡，从而去除了模具氧化物层。因此，防止了由于潮湿蚀刻剂的渗透而导致的绝缘层的无意蚀刻，导致更坚固，更稳定的存储节点结构。

9. 发明授权

US07247541B2 Method of manufacturing a semiconductor memory device including a transistor 失效
标题翻译：制造包括晶体管的半导体存储器件的方法
公开(公告)号：US07247541B2
公开(公告)日：2007-07-24
申请号：US11171710
申请日：2005-06-30
申请人： Jin-Woo Lee , Cheol-Ju Yun , Hyeoung-Won Seo
发明人： Jin-Woo Lee , Cheol-Ju Yun , Hyeoung-Won Seo
IPC分类号： H01L21/336
CPC分类号： H01L27/10814 , H01L27/10823 , H01L27/10852 , H01L27/10873 , H01L27/10876 , H01L27/10885 , H01L27/10888 , H01L28/91 , H01L29/6659
摘要： A semiconductor device comprises a plurality of gate structures formed on a substrate, a gate spacer formed on a sidewall of the gate structures, a semiconductor pattern formed on the substrate between the gate structures, a first impurity region and a second impurity region formed in the semiconductor pattern and at surface portions of the substrate, respectively, wherein the first and second impurity regions include a first conductive type impurity, and a channel doping region surrounding the first impurity region, wherein the channel doping region includes a second conductive type impurity.
摘要翻译：半导体器件包括形成在衬底上的多个栅极结构，形成在栅极结构的侧壁上的栅极间隔物，形成在栅极结构之间的衬底上的半导体图案，形成在栅极结构中的第一杂质区域和第二杂质区域半导体图案和衬底的表面部分，其中第一和第二杂质区域包括第一导电类型杂质和围绕第一杂质区的沟道掺杂区域，其中沟道掺杂区域包括第二导电类型杂质。

10. 发明授权

US07180118B2 Semiconductor device including storage node and method of manufacturing the same 有权
标题翻译：包括存储节点的半导体器件及其制造方法
公开(公告)号：US07180118B2
公开(公告)日：2007-02-20
申请号：US10830895
申请日：2004-04-22
申请人： Chang-Hyun Cho , Tae-Young Chung , Cheol-Ju Yun , Jae-Goo Lee , Ju-Yong Lee
发明人： Chang-Hyun Cho , Tae-Young Chung , Cheol-Ju Yun , Jae-Goo Lee , Ju-Yong Lee
IPC分类号： H01L27/108
CPC分类号： H01L27/10891 , H01L27/0207 , H01L27/10814 , H01L27/10855 , H01L28/91
摘要： A semiconductor device including storage nodes and a method of manufacturing the same: The method includes forming an insulating layer and an etch stop layer on a semiconductor substrate; forming storage node contact bodies to be electrically connected to the semiconductor substrate by penetrating the insulating layer and the etch stop layer; forming landing pads on the etch stop layer to be electrically connected to the storage node contact bodies, respectively; and forming storage nodes on the landing pads, respectively, the storage nodes of which outward sidewalls are completely exposed and which are arranged at an angle to each other.
摘要翻译：一种包括存储节点的半导体器件及其制造方法，该方法包括在半导体衬底上形成绝缘层和蚀刻停止层; 通过穿透所述绝缘层和所述蚀刻停止层形成要与所述半导体衬底电连接的存储节点接触体; 在所述蚀刻停止层上形成分别电连接到所述存储节点接触体的着陆焊盘; 以及分别在着陆焊盘上形成存储节点，其外侧壁完全暴露的存储节点和彼此成角度地布置。

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