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1. 发明授权

US07504333B2 Method of forming bit line of semiconductor device 有权
标题翻译：形成半导体器件位线的方法
公开(公告)号：US07504333B2
公开(公告)日：2009-03-17
申请号：US11614082
申请日：2006-12-21
申请人： Cheol Mo Jeong , Whee Won Cho , Eun Soo Kim , Seung Hee Hong
发明人： Cheol Mo Jeong , Whee Won Cho , Eun Soo Kim , Seung Hee Hong
IPC分类号： H01L21/20
CPC分类号： H01L21/76864 , H01L21/28562 , H01L21/28568 , H01L21/76846 , H01L21/76876
摘要： A method of forming a conductive structure (e.g., bit line) of a semiconductor device includes forming a barrier metal layer on a semiconductor substrate in which structures are formed. An amorphous titanium carbon nitride layer is formed on the barrier metal layer. A tungsten seed layer is formed on the amorphous titanium carbon nitride layer under an atmosphere including a boron gas. A tungsten layer is formed on the tungsten seed layer, thus forming a bit line.
摘要翻译：形成半导体器件的导电结构（例如位线）的方法包括在形成结构的半导体衬底上形成阻挡金属层。在阻挡金属层上形成非晶氮化钛层。在包含硼气体的气氛下，在非晶态氮化钛层上形成钨种子层。在钨籽晶层上形成钨层，形成位线。

2. 发明申请

US20080003796A1 METHOD OF FORMING BIT LINE OF SEMICONDUCTOR DEVICE 有权
标题翻译：形成半导体器件位线的方法
公开(公告)号：US20080003796A1
公开(公告)日：2008-01-03
申请号：US11614082
申请日：2006-12-21
申请人： Cheol Mo JEONG , Whee Won Cho , Eun Soo Kim , Seung Hee Hong
发明人： Cheol Mo JEONG , Whee Won Cho , Eun Soo Kim , Seung Hee Hong
IPC分类号： H01L21/44
CPC分类号： H01L21/76864 , H01L21/28562 , H01L21/28568 , H01L21/76846 , H01L21/76876
摘要： A method of forming a conductive structure (e.g., bit line) of a semiconductor device includes forming a barrier metal layer on a semiconductor substrate in which structures are formed. An amorphous titanium carbon nitride layer is formed on the barrier metal layer. A tungsten seed layer is formed on the amorphous titanium carbon nitride layer under an atmosphere including a boron gas. A tungsten layer is formed on the tungsten seed layer, thus forming a bit line.
摘要翻译：形成半导体器件的导电结构（例如位线）的方法包括在形成结构的半导体衬底上形成阻挡金属层。在阻挡金属层上形成非晶氮化钛层。在包含硼气体的气氛下，在非晶态氮化钛层上形成钨种子层。在钨籽晶层上形成钨层，形成位线。

3. 发明授权

US07462536B2 Method of forming bit line of semiconductor memory device 有权
标题翻译：形成半导体存储器件位线的方法
公开(公告)号：US07462536B2
公开(公告)日：2008-12-09
申请号：US11680500
申请日：2007-02-28
申请人： Cheol Mo Jeong , Whee Won Cho , Jung Geun Kim , Seung Hee Hong
发明人： Cheol Mo Jeong , Whee Won Cho , Jung Geun Kim , Seung Hee Hong
IPC分类号： H01L21/336
CPC分类号： H01L21/7684 , H01L27/10885
摘要： A method of forming a bit line of a semiconductor memory device is performed as follows. A first interlayer insulating layer is formed over a semiconductor substrate in which an underlying structure is formed. A region of the first interlayer insulating layer is etched to form contact holes through which a contact region of the semiconductor substrate is exposed. A low-resistance tungsten layer is deposited on the entire surface including the contact holes, thus forming contacts. A CMP process is performed in order to mitigate surface roughness of the low-resistance tungsten layer. The low-resistance tungsten layer on the interlayer insulating layer is patterned in a bit line metal line pattern, forming a bit line.
摘要翻译：如下进行形成半导体存储器件的位线的方法。第一层间绝缘层形成在形成下面的结构的半导体衬底上。蚀刻第一层间绝缘层的区域以形成暴露半导体衬底的接触区域的接触孔。在包括接触孔的整个表面上沉积低电阻钨层，从而形成接触。执行CMP工艺以减轻低电阻钨层的表面粗糙度。将层间绝缘层上的低电阻钨层图案化为位线金属线图案，形成位线。

4. 发明申请

US20080057688A1 METHOD OF FORMING BIT LINE OF SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：形成半导体存储器件位线的方法
公开(公告)号：US20080057688A1
公开(公告)日：2008-03-06
申请号：US11680500
申请日：2007-02-28
申请人： Cheol Mo JEONG , Whee Won Cho , Jung Geun Kim , Seung Hee Hong
发明人： Cheol Mo JEONG , Whee Won Cho , Jung Geun Kim , Seung Hee Hong
IPC分类号： H01L21/3205
CPC分类号： H01L21/7684 , H01L27/10885
摘要： A method of forming a bit line of a semiconductor memory device is performed as follows. A first interlayer insulating layer is formed over a semiconductor substrate in which an underlying structure is formed. A region of the first interlayer insulating layer is etched to form contact holes through which a contact region of the semiconductor substrate is exposed. A low-resistance tungsten layer is deposited on the entire surface including the contact holes, thus forming contacts. A CMP process is performed in order to mitigate surface roughness of the low-resistance tungsten layer. The low-resistance tungsten layer on the interlayer insulating layer is patterned in a bit line metal line pattern, forming a bit line.
摘要翻译：如下进行形成半导体存储器件的位线的方法。第一层间绝缘层形成在形成下面的结构的半导体衬底上。蚀刻第一层间绝缘层的区域以形成暴露半导体衬底的接触区域的接触孔。在包括接触孔的整个表面上沉积低电阻钨层，从而形成接触。执行CMP工艺以减轻低电阻钨层的表面粗糙度。将层间绝缘层上的低电阻钨层图案化为位线金属线图案，形成位线。

5. 发明申请

US20090001583A1 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE 审中-公开
标题翻译：制造半导体器件的方法
公开(公告)号：US20090001583A1
公开(公告)日：2009-01-01
申请号：US12019945
申请日：2008-01-25
申请人： Cheol Mo Jeong , Whee Won Cho , Seung Hee Hong
发明人： Cheol Mo Jeong , Whee Won Cho , Seung Hee Hong
IPC分类号： H01L21/768 , H01L23/52
CPC分类号： H01L23/53266 , H01L21/76846 , H01L21/76856 , H01L23/5226 , H01L2924/0002 , H01L2924/00
摘要： The present invention relates to a semiconductor device and a method of fabricating the same. In an embodiment of the present invention, an insulating layer in which contact holes are formed is formed over a semiconductor substrate in which lower metal lines are formed. A barrier metal layer, having a stack structure of a first tungsten (W) layer and a tungsten nitride (WN) layer, is formed within the contact holes. Contact plugs are formed within the contact holes.
摘要翻译：半导体器件及其制造方法技术领域本发明涉及半导体器件及其制造方法。在本发明的一个实施例中，形成有接触孔的绝缘层形成在形成下部金属线的半导体衬底上。在接触孔内形成具有第一钨（W）层和氮化钨（WN）层的堆叠结构的阻挡金属层。接触塞形成在接触孔内。

6. 发明申请

US20080003823A1 Method of manufacturing semiconductor device 审中-公开
标题翻译：制造半导体器件的方法
公开(公告)号：US20080003823A1
公开(公告)日：2008-01-03
申请号：US11647765
申请日：2006-12-29
申请人： Whee Won Cho , Seung Hee Hong , Suk Joong Kim , Cheol Mo Jeong
发明人： Whee Won Cho , Seung Hee Hong , Suk Joong Kim , Cheol Mo Jeong
IPC分类号： H01L21/44 , H01L21/465
CPC分类号： H01L21/76829 , H01L21/76802 , H01L23/5222 , H01L2924/0002 , H01L2924/00
摘要： A method of manufacturing a semiconductor device includes the steps of forming an interlayer insulating layer and an etch-stop nitride layer over a semiconductor substrate, etching the etch-stop nitride layer and the interlayer insulating layer to form contact holes, forming contacts in the contact holes, forming an oxide layer on the entire surface including the contacts, etching the oxide layer using the etch-stop nitride layer as a target, thus forming trenches through which the contacts and the etch-stop nitride layer adjacent to the contacts are exposed, and forming bit lines in the trenches.
摘要翻译：一种制造半导体器件的方法包括以下步骤：在半导体衬底上形成层间绝缘层和蚀刻停止氮化物层，蚀刻蚀刻停止氮化物层和层间绝缘层以形成接触孔，在触点中形成触点在包括触点的整个表面上形成氧化物层，使用蚀刻 - 停留氮化物层作为靶蚀刻氧化层，从而形成沟槽，触点和与触点相邻的蚀刻 - 停止氮化物层通过该沟槽暴露，并在沟槽中形成位线。

7. 发明申请

US20080003742A1 METHOD OF MANUFACTURING FLASH MEMORY DEVICE 失效
标题翻译：制造闪存存储器件的方法
公开(公告)号：US20080003742A1
公开(公告)日：2008-01-03
申请号：US11567218
申请日：2006-12-06
申请人： Whee Won Cho , Seung Hee Hong , Seong Hwan Myung , Eun Soo Kim
发明人： Whee Won Cho , Seung Hee Hong , Seong Hwan Myung , Eun Soo Kim
IPC分类号： H01L21/336
CPC分类号： H01L27/11521
摘要： A method of manufacturing flash memory devices increases a coupling ratio by increasing the height of a floating gate externally projecting from an isolation layer. A portion of the isolation layer between the floating gates is etched so that a control gate to be formed subsequently is located between the floating gates. Accordingly, an interference phenomenon can be reduced.
摘要翻译：制造闪速存储器件的方法通过增加从隔离层外部突出的浮动栅极的高度来增加耦合比。蚀刻浮置栅极之间的隔离层的一部分，使得随后形成的控制栅极位于浮置栅极之间。因此，可以降低干扰现象。

8. 发明授权

US07560340B2 Method of manufacturing flash memory device 失效
标题翻译：制造闪存设备的方法
公开(公告)号：US07560340B2
公开(公告)日：2009-07-14
申请号：US11567218
申请日：2006-12-06
申请人： Whee Won Cho , Seung Hee Hong , Seong Hwan Myung , Eun Soo Kim
发明人： Whee Won Cho , Seung Hee Hong , Seong Hwan Myung , Eun Soo Kim
IPC分类号： H01L21/336
CPC分类号： H01L27/11521
摘要： A method of manufacturing flash memory devices increases a coupling ratio by increasing the height of a floating gate externally projecting from an isolation layer. A portion of the isolation layer between the floating gates is etched so that a control gate to be formed subsequently is located between the floating gates. Accordingly, an interference phenomenon can be reduced.
摘要翻译：制造闪速存储器件的方法通过增加从隔离层外部突出的浮动栅极的高度来增加耦合比。蚀刻浮置栅极之间的隔离层的一部分，使得随后形成的控制栅极位于浮置栅极之间。因此，可以降低干扰现象。

9. 发明申请

US20090004814A1 METHOD OF FABRICATING FLASH MEMORY DEVICE 失效
标题翻译：制造闪存存储器件的方法
公开(公告)号：US20090004814A1
公开(公告)日：2009-01-01
申请号：US11964298
申请日：2007-12-26
申请人： Eun Soo Kim , Whee Won Cho , Seung Hee Hong
发明人： Eun Soo Kim , Whee Won Cho , Seung Hee Hong
IPC分类号： H01L21/76
CPC分类号： H01L27/11524 , H01L27/11521
摘要： The invention relates to a method of fabricating a flash memory device. According to the method, select transistors and memory cells are formed on, and junctions are formed in a semiconductor substrate. The semiconductor substrate between a select transistor and an adjacent memory cell are over etched using a hard mask pattern. Accordingly, migration of electrons can be prohibited and program disturbance characteristics can be improved. Further, a void is formed between the memory cells. Accordingly, an interference phenomenon between the memory cells can be reduced and, therefore, the reliability of a flash memory device can be improved.
摘要翻译：本发明涉及一种制造闪速存储器件的方法。根据该方法，在半导体衬底中形成选择晶体管和存储单元，并且形成结。选择晶体管和相邻存储单元之间的半导体衬底使用硬掩模图案过蚀刻。因此，可以禁止电子的迁移，并且可以提高程序干扰特性。此外，在存储单元之间形成空隙。因此，可以减少存储单元之间的干扰现象，因此可以提高闪存器件的可靠性。

10. 发明授权

US07682900B2 Method of fabricating flash memory device 失效
标题翻译：制造闪存设备的方法
公开(公告)号：US07682900B2
公开(公告)日：2010-03-23
申请号：US11964298
申请日：2007-12-26
申请人： Eun Soo Kim , Whee Won Cho , Seung Hee Hong
发明人： Eun Soo Kim , Whee Won Cho , Seung Hee Hong
IPC分类号： H01L21/336
CPC分类号： H01L27/11524 , H01L27/11521
摘要： The invention relates to a method of fabricating a flash memory device. According to the method, select transistors and memory cells are formed on, and junctions are formed in a semiconductor substrate. The semiconductor substrate between a select transistor and an adjacent memory cell are over etched using a hard mask pattern. Accordingly, migration of electrons can be prohibited and program disturbance characteristics can be improved. Further, a void is formed between the memory cells. Accordingly, an interference phenomenon between the memory cells can be reduced and, therefore, the reliability of a flash memory device can be improved.
摘要翻译：本发明涉及一种制造闪速存储器件的方法。根据该方法，在半导体衬底中形成选择晶体管和存储单元，并且形成结。选择晶体管和相邻存储单元之间的半导体衬底使用硬掩模图案过蚀刻。因此，可以禁止电子的迁移，并且可以提高程序干扰特性。此外，在存储单元之间形成空隙。因此，可以减少存储单元之间的干扰现象，因此可以提高闪存器件的可靠性。

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