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1. 发明授权

US07620826B2 Thermal throttling duty estimation methods and systems for a CPU 有权
标题翻译：用于CPU的热节流负荷估计方法和系统
公开(公告)号：US07620826B2
公开(公告)日：2009-11-17
申请号：US11463027
申请日：2006-08-08
申请人： Cheng-Wei Huang , Chia-Ming Hsu , Hao-Lin Lin , Wen-Juin Huang
发明人： Cheng-Wei Huang , Chia-Ming Hsu , Hao-Lin Lin , Wen-Juin Huang
IPC分类号： G06F1/00 , G06F1/26 , G01R21/00
CPC分类号： G06F1/206
摘要： Thermal throttling duty estimation methods for a CPU (Central Processing Unit) in a computer system are provided. The temperature of a CPU is highly related to the CPU performance. CPU temperature data (CPUT) is first acquired. A thermal throttle duty (TTD) is then calculated according to the acquired CPUT. Thereafter, the calculated TTD can be sent to the CPU and the CPU performance is accordingly adjusted.
摘要翻译：提供了一种用于计算机系统中的CPU（中央处理单元）的热节流负荷估计方法。 CPU的温度与CPU性能高度相关。首先采集CPU温度数据（CPUT）。然后根据获得的CPUT计算热节流阀（TTD）。此后，可以将计算出的TTD发送到CPU，并相应地调整CPU性能。

2. 发明申请

US20070220288A1 THERMAL THROTTLING DUTY ESTIMATION METHODS AND SYSTEMS FOR A CPU 有权
标题翻译：一种CPU的热轴承估计方法和系统
公开(公告)号：US20070220288A1
公开(公告)日：2007-09-20
申请号：US11463027
申请日：2006-08-08
申请人： Cheng-Wei Huang , Chia-Ming Hsu , Hao-Lin Lin , Wen-Juin Huang
发明人： Cheng-Wei Huang , Chia-Ming Hsu , Hao-Lin Lin , Wen-Juin Huang
IPC分类号： G06F1/00
CPC分类号： G06F1/206
摘要： Thermal throttling duty estimation methods for a CPU (Central Processing Unit) in a computer system are provided. The temperature of a CPU is highly related to the CPU performance. CPU temperature data (CPUT) is first acquired. A thermal throttle duty (TTD) is then calculated according to the acquired CPUT. Thereafter, the calculated TTD can be sent to the CPU and the CPU performance is accordingly adjusted.
摘要翻译：提供了一种用于计算机系统中的CPU（中央处理单元）的热节流负荷估计方法。 CPU的温度与CPU性能高度相关。首先采集CPU温度数据（CPUT）。然后根据获得的CPUT计算热节流阀（TTD）。此后，可以将计算出的TTD发送到CPU，并相应地调整CPU性能。

3. 发明申请

US20080018651A1 Method and system for capturing image frame 审中-公开
标题翻译：拍摄图像帧的方法和系统
公开(公告)号：US20080018651A1
公开(公告)日：2008-01-24
申请号：US11522900
申请日：2006-09-19
申请人： Wen-Juin Huang , Chung-Ching Huang , Hao-Lin Lin
发明人： Wen-Juin Huang , Chung-Ching Huang , Hao-Lin Lin
IPC分类号： G06F15/00
CPC分类号： G06F11/0787 , G06F11/0706
摘要： A method for capturing an image data from a frame buffer of a computer system takes advantage of a system management interrupt service optionally triggered. If a storage unit functions normally when the computer system fails to work normally, store the image data in the frame buffer into the storage unit. Otherwise, temporarily store the image data in a buffer unit, and then store it in a NVRAM. Then restart the storage unit and restore the image data in the buffer unit into the storage unit. At last, restart the computer system.
摘要翻译：用于从计算机系统的帧缓冲器捕获图像数据的方法利用可选地触发的系统管理中断服务。如果计算机系统无法正常工作时存储单元正常工作，则将帧缓冲区中的图像数据存储到存储单元中。否则，将图像数据临时存储在缓冲单元中，然后将其存储在NVRAM中。然后重新启动存储单元，并将缓冲单元中的图像数据恢复到存储单元中。最后重新启动计算机系统。

4. 发明申请

US20070208929A1 DEVICE INFORMATION MANAGEMENTS SYSTEMS AND METHODS 审中-公开
标题翻译：设备信息管理系统和方法
公开(公告)号：US20070208929A1
公开(公告)日：2007-09-06
申请号：US11560924
申请日：2006-11-17
申请人： Hao-Lin Lin , Chung-Ching Huang
发明人： Hao-Lin Lin , Chung-Ching Huang
IPC分类号： G06F9/00
CPC分类号： G06F9/4411
摘要： A device information management system comprises an application device and a BIOS ROM. The BIOS ROM comprises at least one specific region storing device information for the application device. The specific region is not used by a BIOS and not within a calculation range for checksum calculation. The BIOS ROM further comprises an index recording an address of the specific region. The application device reads the index from the BIOS ROM, and reads the device information from the specific region according to the index.
摘要翻译：设备信息管理系统包括应用设备和BIOS ROM。 BIOS ROM包括用于应用设备的至少一个特定区域存储设备信息。特定区域不被BIOS使用，不在校验和计算的计算范围内。 BIOS ROM还包括记录特定区域的地址的索引。应用程序设备从BIOS ROM读取索引，并根据索引从特定区域读取设备信息。

5. 发明授权

US07930532B2 Systems and methods for basic input output system (BIOS) management 有权
标题翻译：基本输入输出系统（BIOS）管理系统和方法
公开(公告)号：US07930532B2
公开(公告)日：2011-04-19
申请号：US11861335
申请日：2007-09-26
申请人： Hao-Lin Lin , Hsiao-Fung Chou
发明人： Hao-Lin Lin , Hsiao-Fung Chou
IPC分类号： G06F9/00 , G06F15/177
CPC分类号： G06F13/4072
摘要： An embodiment of a computer system comprises a south-bridge. The south-bridge comprises a controller including a buffer for communicating with electronic devices. When detecting that a Reset# signal is asserted, the buffer is set to a Hi-Impedance state to separate the controller from the electronic device. The Reset# signal indicates a full system reset.
摘要翻译：计算机系统的一个实施例包括一个南桥。南桥包括一个包括与电子设备进行通信的缓冲器的控制器。当检测到Reset＃信号被断言时，缓冲器被设置为Hi-Impedance状态以将控制器与电子设备分离。 Reset＃信号表示完整的系统复位。

6. 发明申请

US20100131748A1 COMPUTER SYSTEM WITH REDUCED STORAGE DEVICE AND ASSOCIATED BOOTING METHOD 有权
标题翻译：具有减少存储设备的计算机系统和相关的打击方法
公开(公告)号：US20100131748A1
公开(公告)日：2010-05-27
申请号：US12624846
申请日：2009-11-24
申请人： Hao-Lin Lin
发明人： Hao-Lin Lin
IPC分类号： G06F15/177 , G06F12/00
CPC分类号： G06F3/0658 , G06F3/0625 , G06F3/0626 , G06F3/0679 , Y02D10/154
摘要： A computer system with integrated storage device for storing both a basic input/output system (BIOS) code and an operating system (OS) code and an associated booting method are provided. The computer system includes a central processing unit, a storage device controller and the storage device. The BIOS code and the OS code are stored in an invisible are and a visible area of the storage device, respectively. At first, the storage device controller is activated to read data from an architecture information area of the storage device to perform initialization. Then, the initialized storage device controller converts a read-only memory access command issued from the central processing unit into a suitable format to control loading of the BIOS code from the invisible area. At last, the storage device controller controls loading of the OS code from the visible area to finish the booting of the computer system.
摘要翻译：提供一种具有用于存储基本输入/输出系统（BIOS）代码和操作系统（OS）代码和相关联的引导方法的集成存储设备的计算机系统。计算机系统包括中央处理单元，存储设备控制器和存储设备。 BIOS代码和OS代码分别存储在存储设备的不可见区域和可见区域中。首先，存储设备控制器被激活以从存储设备的架构信息区域读取数据以执行初始化。然后，初始化的存储装置控制器将从中央处理单元发出的只读存储器访问命令转换成适当的格式，以控制来自不可见区域的BIOS代码的加载。最后，存储设备控制器控制OS可视区域的加载，完成计算机系统的启动。

7. 发明授权

US08195930B2 Computer system with reduced storage device and associated booting method 有权
标题翻译：具有减少存储设备和相关引导方法的计算机系统
公开(公告)号：US08195930B2
公开(公告)日：2012-06-05
申请号：US12624846
申请日：2009-11-24
申请人： Hao-Lin Lin
发明人： Hao-Lin Lin
IPC分类号： G06F9/00 , G06F13/28 , G06F13/42 , G06F12/00
CPC分类号： G06F3/0658 , G06F3/0625 , G06F3/0626 , G06F3/0679 , Y02D10/154
摘要： A computer system with integrated storage device for storing both a basic input/output system (BIOS) code and an operating system (OS) code and an associated booting method are provided. The computer system includes a central processing unit, a storage device controller and the storage device. The BIOS code and the OS code are stored in an invisible are and a visible area of the storage device, respectively. At first, the storage device controller is activated to read data from an architecture information area of the storage device to perform initialization. Then, the initialized storage device controller converts a read-only memory access command issued from the central processing unit into a suitable format to control loading of the BIOS code from the invisible area. At last, the storage device controller controls loading of the OS code from the visible area to finish the booting of the computer system.
摘要翻译：提供一种具有用于存储基本输入/输出系统（BIOS）代码和操作系统（OS）代码和相关联的引导方法的集成存储设备的计算机系统。计算机系统包括中央处理单元，存储设备控制器和存储设备。 BIOS代码和OS代码分别存储在存储设备的不可见区域和可见区域中。首先，存储设备控制器被激活以从存储设备的架构信息区域读取数据以执行初始化。然后，初始化的存储装置控制器将从中央处理单元发出的只读存储器访问命令转换成适当的格式，以控制来自不可见区域的BIOS代码的加载。最后，存储设备控制器控制OS可视区域的加载，完成计算机系统的启动。

8. 发明申请

US20100153601A1 METHOD FOR PREVENTING TRANSACTION COLLISION ON BUS AND COMPUTER SYSTEM UTILIZING THE SAME 有权
标题翻译：用于预防总线和计算机系统的交互冲突的方法
公开(公告)号：US20100153601A1
公开(公告)日：2010-06-17
申请号：US12402635
申请日：2009-03-12
申请人： Hao-Lin Lin
发明人： Hao-Lin Lin
IPC分类号： G06F13/00
CPC分类号： G06F13/376
摘要： A computer system is provided. The computer system includes a bus, a first master device, a second master device and a processor. The bus has a data line and a clock line. The first master device is coupled to the bus, detects a start phase of a first transaction on the data line, issues an interrupt message upon the detection of the start phase, and triggers a second transaction in response to a transaction indication message. The processor is coupled to the first master device, receives the interrupt message, and transmits the transaction indication message after a predetermined time interval upon reception of the interrupt message. The second master device is coupled to the bus and triggers the first transaction. The first transaction is finished within the predetermined time interval.
摘要翻译：提供计算机系统。计算机系统包括总线，第一主设备，第二主设备和处理器。总线有数据线和时钟线。第一主设备耦合到总线，检测数据线上的第一事务的起始阶段，在检测到起始阶段时发出中断消息，并响应于事务指示消息触发第二事务。处理器耦合到第一主设备，接收中断消息，并且在接收到中断消息之后在预定时间间隔之后发送交易指示消息。第二主设备耦合到总线并触发第一事务。第一个事务在预定的时间间隔内完成。

9. 发明授权

US07296185B2 Device for debugging and method thereof 有权
标题翻译：调试装置及其方法
公开(公告)号：US07296185B2
公开(公告)日：2007-11-13
申请号：US10820768
申请日：2004-04-09
申请人： Chung-Ching Huang , Hao-Lin Lin
发明人： Chung-Ching Huang , Hao-Lin Lin
IPC分类号： G06F11/00
CPC分类号： G06F11/362
摘要： A debugging device and method are provided, including a central processing unit (CPU) connected to a chipset with a system management interrupt pin. The debugging method includes sending out a system management interrupt signal to central processing unit from the system management interrupt pin of the chipset. Then the CPU moves into a system management mode and pops out a debugging operation window for selecting and executing each debugging item. After the execution of each debugging item is completed, the CPU will leave the debugging operation window and return to the next instruction before debugging. After the execution of each debugging item is completed in the debugging operation window, the CPU will return to the operation system and continue the execution of next instruction before debugging. The execution of debugging will not influence the status and the program execution from the operating system. The disclosed debugging method is convenient for executing each debugging item at any time.
摘要翻译：提供了一种调试设备和方法，包括连接到具有系统管理中断引脚的芯片组的中央处理单元（CPU）。调试方法包括从芯片组的系统管理中断引脚向中央处理单元发送系统管理中断信号。然后CPU进入系统管理模式，并弹出一个调试操作窗口，用于选择和执行每个调试项目。每个调试项目的执行完成后，CPU将离开调试操作窗口，并在调试前返回到下一条指令。在调试操作窗口中完成每个调试项目的执行后，CPU将返回到操作系统，并在调试之前继续执行下一条指令。调试的执行不会影响操作系统的状态和程序的执行。所公开的调试方法可以随时执行每个调试项目。

10. 发明授权

US07882290B2 Method for preventing transaction collision on bus and computer system utilizing the same 有权
标题翻译：使用该方法的总线和计算机系统上防止事务冲突的方法
公开(公告)号：US07882290B2
公开(公告)日：2011-02-01
申请号：US12402635
申请日：2009-03-12
申请人： Hao-Lin Lin
发明人： Hao-Lin Lin
IPC分类号： G06F13/00 , G06F13/372
CPC分类号： G06F13/376
摘要： A computer system is provided. The computer system includes a bus, a first master device, a second master device and a processor. The bus has a data line and a clock line. The first master device is coupled to the bus, detects a start phase of a first transaction on the data line, issues an interrupt message upon the detection of the start phase, and triggers a second transaction in response to a transaction indication message. The processor is coupled to the first master device, receives the interrupt message, and transmits the transaction indication message after a predetermined time interval upon reception of the interrupt message. The second master device is coupled to the bus and triggers the first transaction. The first transaction is finished within the predetermined time interval.
摘要翻译：提供计算机系统。计算机系统包括总线，第一主设备，第二主设备和处理器。总线有数据线和时钟线。第一主设备耦合到总线，检测数据线上的第一事务的起始阶段，在检测到起始阶段时发出中断消息，并响应于事务指示消息触发第二事务。处理器耦合到第一主设备，接收中断消息，并且在接收到中断消息之后在预定时间间隔之后发送交易指示消息。第二主设备耦合到总线并触发第一事务。第一个事务在预定的时间间隔内完成。

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