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1. 发明申请

US20070181973A1 CAPACITOR STRUCTURE 审中-公开
标题翻译：电容结构
公开(公告)号：US20070181973A1
公开(公告)日：2007-08-09
申请号：US11307396
申请日：2006-02-06
申请人： Cheng-Chou Hung , Victor Liang , Hua-Chou Tseng , Chih-Yu Tseng
发明人： Cheng-Chou Hung , Victor Liang , Hua-Chou Tseng , Chih-Yu Tseng
IPC分类号： H01L29/00
CPC分类号： H01L23/5223 , H01L28/60 , H01L2924/0002 , H01L2924/00
摘要： A capacitor structure including a plurality of conductive layers, a dielectric layer and a plurality of contacts is disclosed. The conductive layers are stacked, and each conductive layer has a first conductive pattern and a second conductive pattern. The dielectric layer is disposed between the first conductive pattern and the second conductive pattern and between two adjacent conductive layers. The contacts are disposed in the dielectric layer, and electrically connected to the first conductive patterns in two adjacent conductive layers and electrically connected to the second conductive patterns in two adjacent conductive layers. Wherein, the contact electrically connecting to the first conductive patterns in two adjacent conducive layers is a first strip contact, which extends between the first conductive patterns in two adjacent conductive layers, and the boundary of the first strip contact is located within the boundary of the first conductive pattern.
摘要翻译：公开了一种包括多个导电层，电介质层和多个触点的电容器结构。导电层被堆叠，并且每个导电层具有第一导电图案和第二导电图案。电介质层设置在第一导电图案和第二导电图案之间以及两个相邻的导电层之间。触点设置在电介质层中，并且电连接到两个相邻导电层中的第一导电图案并且电连接到两个相邻导电层中的第二导电图案。其中，电连接到两个相邻导电层中的第一导电图案的触点是在两个相邻的导电层中在第一导电图案之间延伸的第一条形接触，并且第一条带接触的边界位于第一导电图案。

2. 发明授权

US08507987B2 Radio frequency device and method for fabricating the same 有权
标题翻译：射频装置及其制造方法
公开(公告)号：US08507987B2
公开(公告)日：2013-08-13
申请号：US12563434
申请日：2009-09-21
申请人： Sheng-Yi Huang , Cheng-Chou Hung , Tzung-Lin Li , Chin-Lan Tseng , Victor-Chiang Liang , Chih-Yu Tseng
发明人： Sheng-Yi Huang , Cheng-Chou Hung , Tzung-Lin Li , Chin-Lan Tseng , Victor-Chiang Liang , Chih-Yu Tseng
IPC分类号： H01L29/66 , H01L21/336
CPC分类号： H01L29/6656 , H01L21/823425 , H01L21/823437 , H01L21/823456 , H01L29/6659 , H01L29/7833
摘要： A radio frequency (RF) device that can achieve high frequency response while maintaining high output impedance and high breakdown voltage includes a substrate, a gate, at least a dummy gate, at least a doped region, a source region and a drain region. The substrate includes a well of first type and a well of second type. The well of second type is adjacent to the well of first type.
摘要翻译：能够实现高频响应同时保持高输出阻抗和高击穿电压的射频（RF）器件包括衬底，栅极，至少伪栅极，至少掺杂区域，源极区域和漏极区域。衬底包括第一类型的阱和第二类型的阱。第二类井与第一类井相邻。

3. 发明申请

US20100200947A1 DIE SEAL RING 有权
标题翻译： DIE密封圈
公开(公告)号：US20100200947A1
公开(公告)日：2010-08-12
申请号：US12366654
申请日：2009-02-06
申请人： Cheng-Chou Hung , Victor-Chiang Liang , Jui-Meng Jao , Cheng-Hung Li , Sheng-Yi Huang , Tzung-Lin Li , Huai-Wen Zhang , Chih-Yu Tseng
发明人： Cheng-Chou Hung , Victor-Chiang Liang , Jui-Meng Jao , Cheng-Hung Li , Sheng-Yi Huang , Tzung-Lin Li , Huai-Wen Zhang , Chih-Yu Tseng
IPC分类号： H01L29/06
CPC分类号： H01L23/585 , H01L21/76229 , H01L2924/0002 , H01L2924/00
摘要： A die seal ring disposed outside of a die region of a semiconductor substrate is disclosed. The die seal ring includes a first isolation structure, a second isolation structure, and at least one third isolation structure disposed between the first isolation structure and the second isolation structure; a plurality of first regions between the first isolation structure, the second isolation structure and the third isolation structure; a second region under the first region and the third isolation structure; and a third region under the first isolation structure.
摘要翻译：公开了设置在半导体衬底的管芯区域的外侧的管芯密封环。模具密封环包括第一隔离结构，第二隔离结构以及设置在第一隔离结构和第二隔离结构之间的至少一个第三隔离结构; 所述第一隔离结构，所述第二隔离结构和所述第三隔离结构之间的多个第一区域; 第一区域和第三隔离结构之下的第二区域; 和第一隔离结构下的第三区域。

4. 发明申请

US20100109080A1 PSEUDO-DRAIN MOS TRANSISTOR 审中-公开
标题翻译： PSEUDO-DRAIN MOS晶体管
公开(公告)号：US20100109080A1
公开(公告)日：2010-05-06
申请号：US12264912
申请日：2008-11-05
申请人： Sheng-Yi Huang , Cheng-Chou Hung , Tzung-Lin Li , Chin-Lan Tseng , Victor-Chiang Liang , Chih-Yu Tseng
发明人： Sheng-Yi Huang , Cheng-Chou Hung , Tzung-Lin Li , Chin-Lan Tseng , Victor-Chiang Liang , Chih-Yu Tseng
IPC分类号： H01L29/78
CPC分类号： H01L29/0847 , H01L29/66659 , H01L29/7835
摘要： A pseudo-drain MOS transistor is disclosed. The transistor includes a semiconductor substrate; a gate structure disposed on the semiconductor substrate; a source, a pseudo-drain, a drain, and a shallow trench isolation disposed in the semiconductor substrate, a p-well disposed in the semiconductor substrate and under the source and the gate structure; and an n-well disposed under the drain. The source and the pseudo-drain are disposed adjacent to two sides of the gate structure and the shallow trench isolation is disposed between the pseudo-drain and the drain, and the n-well is extended toward the pseudo-drain while not reaching the area below the gate structure.
摘要翻译：公开了一种伪漏极MOS晶体管。晶体管包括半导体衬底; 设置在所述半导体基板上的栅极结构; 设置在半导体衬底中的源极，伪漏极，漏极和浅沟槽隔离物，设置在半导体衬底中并在源极和栅极结构之下的p阱; 以及设置在排水管下方的n阱。源极和伪漏极邻近栅极结构的两侧设置，并且浅沟槽隔离设置在伪漏极和漏极之间，并且n阱延伸到伪漏极而不到达区域在门结构之下。

5. 发明申请

US20110068415A1 Radio Frequency Device and Method for Fabricating the Same 有权
标题翻译：射频装置及其制造方法
公开(公告)号：US20110068415A1
公开(公告)日：2011-03-24
申请号：US12563434
申请日：2009-09-21
申请人： Sheng-Yi Huang , Cheng-Chou Hung , Tzung-Lin Li , Chin-Lan Tseng , Victor-Chiang Liang , Chih-Yu Tseng
发明人： Sheng-Yi Huang , Cheng-Chou Hung , Tzung-Lin Li , Chin-Lan Tseng , Victor-Chiang Liang , Chih-Yu Tseng
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/6656 , H01L21/823425 , H01L21/823437 , H01L21/823456 , H01L29/6659 , H01L29/7833
摘要： A radio frequency (RF) device that can achieve high frequency response while maintaining high output impedance and high breakdown voltage includes a substrate, a gate, at least a dummy gate, at least a doped region, a source region and a drain region. The substrate includes a well of first type and a well of second type. The well of second type is adjacent to the well of first type.
摘要翻译：能够实现高频响应同时保持高输出阻抗和高击穿电压的射频（RF）器件包括衬底，栅极，至少伪栅极，至少掺杂区域，源极区域和漏极区域。衬底包括第一类型的阱和第二类型的阱。第二类井与第一类井相邻。

6. 发明授权

US08357988B2 Die seal ring 有权
标题翻译：模具密封圈
公开(公告)号：US08357988B2
公开(公告)日：2013-01-22
申请号：US12366654
申请日：2009-02-06
申请人： Cheng-Chou Hung , Victor-Chiang Liang , Jui-Meng Jao , Cheng-Hung Li , Sheng-Yi Huang , Tzung-Lin Li , Huai-Wen Zhang , Chih-Yu Tseng
发明人： Cheng-Chou Hung , Victor-Chiang Liang , Jui-Meng Jao , Cheng-Hung Li , Sheng-Yi Huang , Tzung-Lin Li , Huai-Wen Zhang , Chih-Yu Tseng
IPC分类号： H01L21/70
CPC分类号： H01L23/585 , H01L21/76229 , H01L2924/0002 , H01L2924/00
摘要： A die seal ring disposed outside of a die region of a semiconductor substrate is disclosed. The die seal ring includes a first isolation structure, a second isolation structure, and at least one third isolation structure disposed between the first isolation structure and the second isolation structure; a plurality of first regions between the first isolation structure, the second isolation structure and the third isolation structure; a second region under the first region and the third isolation structure; and a third region under the first isolation structure.
摘要翻译：公开了设置在半导体衬底的管芯区域的外侧的管芯密封环。模具密封环包括第一隔离结构，第二隔离结构以及设置在第一隔离结构和第二隔离结构之间的至少一个第三隔离结构; 所述第一隔离结构，所述第二隔离结构和所述第三隔离结构之间的多个第一区域; 第一区域和第三隔离结构之下的第二区域; 和第一隔离结构下的第三区域。

7. 发明授权

US08637936B2 Metal gate transistor with resistor 有权
标题翻译：带电阻的金属栅极晶体管
公开(公告)号：US08637936B2
公开(公告)日：2014-01-28
申请号：US12566678
申请日：2009-09-25
申请人： Kai-Ling Chiu , Victor-Chiang Liang , Chih-Yu Tseng , Kun-Szu Tseng , Cheng-Wen Fan , Hsin-Kai Chiang , Chih-Chen Hsueh
发明人： Kai-Ling Chiu , Victor-Chiang Liang , Chih-Yu Tseng , Kun-Szu Tseng , Cheng-Wen Fan , Hsin-Kai Chiang , Chih-Chen Hsueh
IPC分类号： H01L27/11
CPC分类号： H01L27/0629 , H01L28/20 , H01L28/24
摘要： A resistor is disclosed. The resistor is disposed on a substrate, in which the resistor includes: a dielectric layer disposed on the substrate; a polysilicon structure disposed on the dielectric layer; two primary resistance structures disposed on the dielectric layer and at two ends of the polysilicon structure; and a plurality of secondary resistance structures disposed on the dielectric layer and interlaced with the polysilicon structures.
摘要翻译：公开了一种电阻器。电阻器设置在基板上，其中电阻器包括：布置在基板上的电介质层; 设置在电介质层上的多晶硅结构; 布置在电介质层上并在多晶硅结构两端的两个初级电阻结构; 以及设置在电介质层上并与多晶硅结构隔行的多个次级电阻结构。

8. 发明申请

US20110292565A1 CAPACITOR STRUCTURE 有权
标题翻译：电容结构
公开(公告)号：US20110292565A1
公开(公告)日：2011-12-01
申请号：US13198286
申请日：2011-08-04
申请人： Kai-Ling Chiu , Victor Chiang Liang , Chih-Yu Tseng , Hui-Sheng Chang , Chia-Te Chien , You-Ren Liu
发明人： Kai-Ling Chiu , Victor Chiang Liang , Chih-Yu Tseng , Hui-Sheng Chang , Chia-Te Chien , You-Ren Liu
IPC分类号： H01G4/30
CPC分类号： H01G4/30 , H01G4/012 , H01G4/232 , H01L23/5222 , H01L2924/0002 , H01L2924/00
摘要： A capacitor structure includes a plurality of conductive line levels located over the substrate. Each of the conductive line levels includes a first conductive line and a second conductive line. The first conductive lines in the conductive line levels form a first conductive line co-plane and the second conductive lines in the conductive line levels form a second conductive line co-plane. A first conductive end is electrically connected to the first conductive lines on the conductive line levels. A second conductive end is electrically connected to the second conductive lines on the conductive line levels. A plurality of vias are located between the neighboring conductive line levels and placed on only one of the first and second conductive line co-planes on a same level.
摘要翻译：电容器结构包括位于衬底上方的多个导线电平。每个导线电平包括第一导线和第二导线。导线电平中的第一导线形成第一导线共面，并且导线电平中的第二导线形成第二导线共平面。第一导电端电连接到导线级上的第一导线。第二导电端电连接到导线上的第二导线。多个通孔位于相邻的导线电平之间，并且仅放置在相同电平上的第一和第二导线共面之一上。

9. 发明申请

US20100328022A1 METHOD FOR FABRICATING METAL GATE AND POLYSILICON RESISTOR AND RELATED POLYSILICON RESISTOR STRUCTURE 有权
标题翻译：制造金属栅和多晶硅电阻的方法及相关多晶硅电阻结构
公开(公告)号：US20100328022A1
公开(公告)日：2010-12-30
申请号：US12490334
申请日：2009-06-24
申请人： Cheng-Wen Fan , Kun-Szu Tseng , Che-Hua Hsu , Chih-Yu Tseng , Victor-Chiang Liang
发明人： Cheng-Wen Fan , Kun-Szu Tseng , Che-Hua Hsu , Chih-Yu Tseng , Victor-Chiang Liang
IPC分类号： H01C1/012 , H01L21/336 , H01L21/02
CPC分类号： H01L27/0629 , H01L28/20 , H01L29/495 , H01L29/4966 , H01L29/66545
摘要： An integrated method includes fabricating a metal gate and a polysilicon resistor structure. A photoresistor layer is defined by an SAB photo mask and covers a part of a polysilicon structure of the polysilicon resistor. When the gate conductor of a poly gate transistor is etched, the part of the polysilicon structure is protected by the patterned photoresistor layer. After the polysilicon resistor and the metal gate are formed. The polysilicon resistor still has sufficient resistance and includes two metal structures for electrical connection.
摘要翻译：集成方法包括制造金属栅极和多晶硅电阻器结构。光电晶体层由SAB光掩模限定并且覆盖多晶硅电阻器的多晶硅结构的一部分。当蚀刻多晶硅晶体管的栅极导体时，多晶硅结构的一部分被图案化的光敏电阻层保护。在形成多晶硅电阻器和金属栅极之后。多晶硅电阻器仍然具有足够的电阻并且包括用于电连接的两个金属结构。

10. 发明授权

US08193900B2 Method for fabricating metal gate and polysilicon resistor and related polysilicon resistor structure 有权
标题翻译：制造金属栅极和多晶硅电阻器及相关多晶硅电阻器结构的方法
公开(公告)号：US08193900B2
公开(公告)日：2012-06-05
申请号：US12490334
申请日：2009-06-24
申请人： Cheng-Wen Fan , Kun-Szu Tseng , Che-Hua Hsu , Chih-Yu Tseng , Victor-Chiang Liang
发明人： Cheng-Wen Fan , Kun-Szu Tseng , Che-Hua Hsu , Chih-Yu Tseng , Victor-Chiang Liang
IPC分类号： H01C1/012
CPC分类号： H01L27/0629 , H01L28/20 , H01L29/495 , H01L29/4966 , H01L29/66545
摘要： An integrated method includes fabricating a metal gate and a polysilicon resistor structure. A photoresistor layer is defined by an SAB photo mask and covers a part of a polysilicon structure of the polysilicon resistor. When the gate conductor of a poly gate transistor is etched, the part of the polysilicon structure is protected by the patterned photoresistor layer. After the polysilicon resistor and the metal gate are formed. The polysilicon resistor still has sufficient resistance and includes two metal structures for electrical connection.
摘要翻译：集成方法包括制造金属栅极和多晶硅电阻器结构。光电晶体层由SAB光掩模限定并且覆盖多晶硅电阻器的多晶硅结构的一部分。当蚀刻多晶硅晶体管的栅极导体时，多晶硅结构的一部分被图案化的光敏电阻层保护。在形成多晶硅电阻器和金属栅极之后。多晶硅电阻器仍然具有足够的电阻并且包括用于电连接的两个金属结构。

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