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1. 发明申请

US20140208085A1 INSTRUCTION AND LOGIC TO EFFICIENTLY MONITOR LOOP TRIP COUNT 有权
标题翻译：指令和逻辑到有效的监视器循环次数
公开(公告)号：US20140208085A1
公开(公告)日：2014-07-24
申请号：US13996861
申请日：2012-03-30
申请人： Jaewoong Chung , Hyunchul Park , Hongbo Rong , Cheng Wang , Youfeng Wu
发明人： Jaewoong Chung , Hyunchul Park , Hongbo Rong , Cheng Wang , Youfeng Wu
IPC分类号： G06F9/32
CPC分类号： G06F9/325 , G06F8/443 , G06F9/30072 , G06F9/3842 , G06F9/3857 , G06F11/3409 , G06F11/348 , G06F2201/88
摘要： Logic and instruction to efficiently monitor loop trip count. Loop trip count information of a loop may be stored in a dedicated hardware buffer. Average loop trip count of the loop may be calculated based on the stored loop trip count information. Based on the average trip count, loop optimizations may be applied or removed from the loop. The stored loop trip count information may include an identifier identifying the loop, a total loop trip count of the loop, and an exit count of the loop.
摘要翻译：有效监控回路行程数的逻辑和指令。循环的循环行程计数信息可以存储在专用硬件缓冲器中。可以基于存储的循环行程计数信息来计算循环的平均循环行程计数。基于平均行程计数，循环优化可以从循环中应用或移除。存储的循环行程计数信息可以包括标识循环的标识符，循环的总循环行程计数以及循环的退出计数。

2. 发明申请

US20150212836A1 CONJUGATE CODE GENERATION FOR EFFICIENT DYNAMIC OPTIMIZATIONS 审中-公开
标题翻译：有效动态优化的合并代码生成
公开(公告)号：US20150212836A1
公开(公告)日：2015-07-30
申请号：US14126894
申请日：2013-10-24
申请人： Hongbo Rong , Hyunchul Park , Cheng Wang , Youfeng Wu
发明人： Hongbo Rong , Hyunchul Park , Cheng Wang , Youfeng Wu
IPC分类号： G06F9/455 , G06F9/45
CPC分类号： G06F9/4552 , G06F8/4442 , G06F8/52 , G06F9/45508 , G06F9/45533
摘要： Methods and apparatus relating to conjugate code generation for efficient dynamic optimizations are described. In an embodiment, a binary code and an intermediate representation (IR) code are generated based at least partially on a source program. The binary code and the intermediate code are transmitted to a virtual machine logic. The binary code and the IR code each include a plurality of regions that are in one-to-one correspondence. Other embodiments are also claimed and described.
摘要翻译：描述了用于有效动态优化的共轭码生成相关的方法和装置。在一个实施例中，至少部分地基于源程序生成二进制代码和中间表示（IR）代码。二进制代码和中间代码被传送到虚拟机逻辑。二进制代码和IR代码每个包括一对一对应的多个区域。还要求保护和描述其它实施例。

3. 发明申请

US20150169226A1 TECHNOLOGIES FOR PERSISTENT MEMORY PROGRAMMING 有权
标题翻译：不间断内存编程技术
公开(公告)号：US20150169226A1
公开(公告)日：2015-06-18
申请号：US14496621
申请日：2014-09-25
申请人： Xipeng Shen , Youfeng Wu , Cheng Wang , Hyunchul Park , Hongbo Rong
发明人： Xipeng Shen , Youfeng Wu , Cheng Wang , Hyunchul Park , Hongbo Rong
IPC分类号： G06F3/06
CPC分类号： G06F12/0238 , G06F2212/7201 , G06F2212/7202 , G06F2212/7207
摘要： Technologies for persistent memory programming include a computing device having a persistent memory including one or more nonvolatile regions. The computing device may assign a virtual memory address of a target location in persistent memory to a persistent memory pointer using persistent pointer strategy, and may dereference the pointer using the same strategy. Persistent pointer strategies include off-holder, ID-in-value, optimistic rectification, and pessimistic rectification. The computing device may log changes to persistent memory during the execution of a data consistency section, and commit changes to the persistent memory when the last data consistency section ends. Data consistency sections may be grouped by log group identifier. Using type metadata stored in the nonvolatile region, the computing device may identify the type of a root object within the nonvolatile region and then recursively identify the type of all objects referenced by the root object. Other embodiments are described and claimed.
摘要翻译：用于持久存储器编程的技术包括具有包括一个或多个非易失性区域的持久存储器的计算设备。计算设备可以使用持久指针策略将永久存储器中的目标位置的虚拟存储器地址分配给持久存储器指针，并且可以使用相同的策略来解除引用。持续指标策略包括持有人，价值观，乐观整改和悲观整改。在执行数据一致性部分期间，计算设备可以将改变记录到持久存储器，并且当最后数据一致性部分结束时，向永久存储器提交更改。数据一致性部分可以按日志组标识符分组。使用存储在非易失性区域中的类型元数据，计算设备可以识别非易失性区域内的根对象的类型，然后递归地标识由根对象引用的所有对象的类型。描述和要求保护其他实施例。

4. 发明申请

US20150277866A1 CO-DESIGNED DYNAMIC LANGUAGE ACCELERATOR FOR A PROCESSOR 有权
标题翻译：用于处理器的CO设计动态语言加速器
公开(公告)号：US20150277866A1
公开(公告)日：2015-10-01
申请号：US14225755
申请日：2014-03-26
申请人： Cheng Wang , Youfeng Wu , Hongbo Rong , Hyunchul Park
发明人： Cheng Wang , Youfeng Wu , Hongbo Rong , Hyunchul Park
IPC分类号： G06F9/45 , G06F9/455
CPC分类号： G06F9/45516 , G06F9/4411 , G06F9/4552 , G06F13/10
摘要： In an embodiment, a processor includes at least one core and a dynamic language accelerator to execute a bytecode responsive to a memory mapped input/output (MMIO) operation on a file descriptor associated with the dynamic language accelerator. The processor may block execution of native code while the dynamic language accelerator executes the bytecode. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，处理器包括至少一个核心和动态语言加速器，以响应于与动态语言加速器相关联的文件描述符的存储器映射的输入/输出（MMIO）操作来执行字节码。当动态语言加速器执行字节码时，处理器可能会阻止本地代码的执行。描述和要求保护其他实施例。

5. 发明申请

US20150039861A1 ALLOCATION OF ALIAS REGISTERS IN A PIPELINED SCHEDULE 有权
标题翻译：在管道附表中分配ALIAS注册
公开(公告)号：US20150039861A1
公开(公告)日：2015-02-05
申请号：US14126466
申请日：2013-05-30
申请人： Hongbo Rong , Cheng Wang , Hyunchul Park , Youfeng Wu
发明人： Hongbo Rong , Cheng Wang , Hyunchul Park , Youfeng Wu
IPC分类号： G06F9/38 , G06F9/30
CPC分类号： G06F9/3838 , G06F8/434 , G06F8/441 , G06F8/443 , G06F9/30127 , G06F9/3017 , G06F9/3834 , G06F9/384
摘要： In an embodiment, a system includes a processor including one or more cores and a plurality of alias registers to store memory range information associated with a plurality of operations of a loop. The memory range information references one or more memory locations within a memory. The system also includes register assignment means for assigning each of the alias registers to a corresponding operation of the loop, where the assignments are made according to a rotation schedule, and one of the alias registers is assigned to a first operation in a first iteration of the loop and to a second operation in a subsequent iteration of the loop. The system also includes the memory coupled to the processor. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，系统包括处理器，其包括一个或多个核和多个别名寄存器，用于存储与循环的多个操作相关联的存储器范围信息。存储器范围信息引用存储器内的一个或多个存储器位置。该系统还包括寄存器分配装置，用于将每个别名寄存器分配给循环的对应操作，其中根据旋转调度进行分配，并且在第一次迭代中将一个别名寄存器分配给第一操作循环和循环的后续迭代中的第二操作。该系统还包括耦合到处理器的存储器。描述和要求保护其他实施例。

6. 发明授权

US09715388B2 Instruction and logic to monitor loop trip count and remove loop optimizations 有权
公开(公告)号：US09715388B2
公开(公告)日：2017-07-25
申请号：US13996861
申请日：2012-03-30
申请人： Jaewoong Chung , Hyunchul Park , Hongbo Rong , Cheng Wang , Youfeng Wu
发明人： Jaewoong Chung , Hyunchul Park , Hongbo Rong , Cheng Wang , Youfeng Wu
IPC分类号： G06F15/00 , G06F7/38 , G06F9/00 , G06F9/44 , G06F9/32 , G06F9/30 , G06F9/38 , G06F11/34 , G06F9/45
CPC分类号： G06F9/325 , G06F8/443 , G06F9/30072 , G06F9/3842 , G06F9/3857 , G06F11/3409 , G06F11/348 , G06F2201/88
摘要： Logic and instruction to monitor loop trip count are disclosed. Loop trip count information of a loop may be stored in a dedicated hardware buffer. Average loop trip count of the loop may be calculated based on the stored loop trip count information. Based on the average trip count, loop optimizations may be removed from the loop. The stored loop trip count information may include an identifier identifying the loop, a total loop trip count of the loop, and an exit count of the loop.

7. 发明申请

US20140359591A1 DYNAMIC OPTIMIZATION OF PIPELINED SOFTWARE 有权
标题翻译：管道软件动态优化
公开(公告)号：US20140359591A1
公开(公告)日：2014-12-04
申请号：US14126463
申请日：2013-05-30
申请人： Hyunchul Park , Hongbo Rong , Youfeng Wu
发明人： Hyunchul Park , Hongbo Rong , Youfeng Wu
IPC分类号： G06F9/45
CPC分类号： G06F8/4452 , G06F8/441 , G06F8/443 , G06F8/4451 , G06F9/3836 , G06F9/384 , G06F9/3863
摘要： In an embodiment, a system includes a processor including at least one core to execute operations of a loop that includes S stages. The system also includes stage insertion means for adding a delay stage to the loop to increase a lifetime of a corresponding register associated with a first variable of the loop and to delay storage of contents of the register. The system also includes a dynamic random access memory (DRAM). Other embodiments are described and claimed.
摘要翻译：在一个实施例中，系统包括处理器，其包括至少一个核，以执行包括S级的循环的操作。该系统还包括阶段插入装置，用于向环路增加延迟级，以增加与循环的第一变量相关联的相应寄存器的寿命并延迟存储寄存器的内容。该系统还包括动态随机存取存储器（DRAM）。描述和要求保护其他实施例。

8. 发明申请

US20140298306A1 SOFTWARE PIPELINING AT RUNTIME 有权
标题翻译：软件管道运行
公开(公告)号：US20140298306A1
公开(公告)日：2014-10-02
申请号：US13853430
申请日：2013-03-29
申请人： Hongbo Rong , Hyunchul Park , Youfeng Wu
发明人： Hongbo Rong , Hyunchul Park , Youfeng Wu
IPC分类号： G06F9/45
CPC分类号： G06F8/4452 , G06F8/433
摘要： Apparatuses and methods may provide for determining a level of performance for processing one or more loops by a dynamic compiler and executing code optimizations to generate a pipelined schedule for the one or more loops that achieves the determined level of performance within a prescribed time period. In one example, a dependence graph may be established for the one or more loops, and each dependence graph may be partitioned into stages based on the level of performance.
摘要翻译：设备和方法可以提供用于通过动态编译器来确定用于处理一个或多个循环的性能水平，并且执行代码优化以生成用于在规定时间段内实现所确定的性能水平的所述一个或多个循环的流水线调度。在一个示例中，可以为一个或多个循环建立依赖图，并且可以基于性能水平将每个依赖图划分成多个阶段。

9. 发明申请

US20160188305A1 TECHNOLOGIES FOR LOW-LEVEL COMPOSABLE HIGH PERFORMANCE COMPUTING LIBRARIES 有权
标题翻译：低水平复合高性能计算机图形技术
公开(公告)号：US20160188305A1
公开(公告)日：2016-06-30
申请号：US14583657
申请日：2014-12-27
申请人： Hongbo Rong , Peng Tu , Tatiana Shpeisman , Hai Liu , Todd A. Anderson , Youfeng Wu , Arthur N. Glew , Paul M. PetersEn , Victor W. Lee , P.G. Lowney , Arch D. Robinson , Cheng Wang
发明人： Hongbo Rong , Peng Tu , Tatiana Shpeisman , Hai Liu , Todd A. Anderson , Youfeng Wu , Arthur N. Glew , Paul M. PetersEn , Victor W. Lee , P.G. Lowney , Arch D. Robinson , Cheng Wang
IPC分类号： G06F9/45 , G06F9/44
CPC分类号： G06F8/43 , G06F8/31 , G06F8/443 , G06F8/4441 , G06F8/453 , G06F8/49 , G06F8/54
摘要： Technologies for generating composable library functions include a first computing device that includes a library compiler configured to compile a composable library and second computing device that includes an application compiler configured to compose library functions of the composable library based on a plurality of abstractions written at different levels of abstractions. For example, the abstractions may include an algorithm abstraction at a high level, a blocked-algorithm abstraction at medium level, and a region-based code abstraction at a low level. Other embodiments are described and claimed herein.
摘要翻译：用于生成可组合库函数的技术包括：第一计算设备，其包括被配置为编译可组合库的库编译器和第二计算设备，所述第二计算设备包括应用编译器，所述应用编译器被配置为基于以不同级别写入的多个抽象来组合所述可组合库的库函数的抽象。例如，抽象可以包括高级别的算法抽象，中等级别的阻塞算法抽象，以及低级别的基于区域的代码抽象。在此描述和要求保护的其它实施例。

10. 发明授权

US08443343B2 Context-sensitive slicing for dynamically parallelizing binary programs 有权
标题翻译：用于动态并行化二进制程序的上下文相关切片
公开(公告)号：US08443343B2
公开(公告)日：2013-05-14
申请号：US12607589
申请日：2009-10-28
申请人： Joseph Blomstedt , Cheng Wang , Youfeng Wu
发明人： Joseph Blomstedt , Cheng Wang , Youfeng Wu
IPC分类号： G06F9/45
CPC分类号： G06F11/3604 , G06F8/433 , G06F8/456
摘要： In one embodiment of the invention a method comprising (1) receiving an unstructured binary code region that is single-threaded; (2) determining a slice criterion for the region; (3) determining a call edge, a return edge, and a fallthrough pseudo-edge for the region based on analysis of the region at a binary level; and (4) determining a context-sensitive slice based on the call edge, the return edge, the fallthrough pseudo-edge, and the slice criterion. Embodiments of the invention may include a program analysis technique that can be used to provide context-sensitive slicing of binary programs for slicing hot regions identified at runtime, with few underlying assumptions about the program from which the binary is derived. Also, in an embodiment a slicing method may include determining a context-insensitive slice, when a time limit is met, by determining the context-insensitive slice while treating call edges as a normal control flow edges.
摘要翻译：在本发明的一个实施例中，一种方法包括（1）接收单线程的非结构化二进制码区域; （2）确定该区域的切片标准; （3）基于二进制级别的区域的分析确定该区域的通话边缘，返回边缘和下降伪边缘; 和（4）基于呼叫边缘，返回边缘，下降伪边缘和切片标准来确定上下文敏感切片。本发明的实施例可以包括程序分析技术，其可以用于提供二进制程序的上下文敏感切片，用于对在运行时识别的热区域进行切片，而关于从其导出二进制的程序的几个基本假设。此外，在一个实施例中，切片方法可以包括当满足时间限制时，通过在将呼叫边缘视为正常控制流边缘的同时确定上下文不敏感切片来确定上下文不敏感切片。

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