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1. 发明授权

US06558181B2 System and method for package socket with embedded power and ground planes 有权
公开(公告)号：US06558181B2
公开(公告)日：2003-05-06
申请号：US09751598
申请日：2000-12-29
申请人： Chee-Yee Chung , David Figueroa , Kris Frutschy , Bob Sankman , Farzaneh Yahyaei-Moayyed
发明人： Chee-Yee Chung , David Figueroa , Kris Frutschy , Bob Sankman , Farzaneh Yahyaei-Moayyed
IPC分类号： H01R13625
CPC分类号： H05K7/1092 , H05K1/0231 , H05K1/141 , Y10T29/49169
摘要： A system and method for embedding power and ground planes in a pin grid array (PGA) socket is provided. Integrated circuit pins are inserted into multiple insertion holes of varying dimensions in the power and ground planes. When the cover of the socket is slidably moved, power pins touch the power plane and ground pins touch the ground plane. Decoupling capacitors are also affixed to the substrate. Thus, the power delivery performance of the overall central processing unit (CPU) package is improved. Moreover, the power and ground planes enhance the mechanical strength of the socket which reduces warpage.

2. 发明授权

US06584685B2 System and method for package socket with embedded power and ground planes 有权
标题翻译：具有嵌入式电源和接地层的封装插座的系统和方法
公开(公告)号：US06584685B2
公开(公告)日：2003-07-01
申请号：US10025257
申请日：2001-12-17
申请人： Chee-Yee Chung , David Figueroa , Kris Frutschy , Bob Sankman , Farzaneh Yahyaei-Moayyed
发明人： Chee-Yee Chung , David Figueroa , Kris Frutschy , Bob Sankman , Farzaneh Yahyaei-Moayyed
IPC分类号： H05K1300
CPC分类号： H05K7/1092 , H05K1/0231 , H05K1/141 , Y10T29/49169
摘要： A system and method for embedding power and ground planes in a pin grid array (PGA) socket is provided. Integrated circuit pins are inserted into multiple insertion holes of varying dimensions in the power and ground planes. When the cover of the socket is slidably moved, power pins touch the power plane and ground pins touch the ground plane. Decoupling capacitors are also affixed to the substrate. Thus, the power delivery performance of the overall central processing unit (CPU) package is improved. Moreover, the power and ground planes enhance the mechanical strength of the socket which reduces warpage.
摘要翻译：提供了一种将电源和接地平面嵌入引脚格阵列（PGA）插座的系统和方法。集成电路引脚插入电源和接地层中不同尺寸的多个插入孔。当插座的盖子可滑动移动时，电源插头触摸电源平面，接地引脚接触地平面。去耦电容器也贴在基板上。因此，整体中央处理单元（CPU）封装的功率传递性能得到改善。此外，电源和接地平面增强了插座的机械强度，减少了翘曲。

3. 发明申请

US20060139847A1 Capacitor design for controlling equivalent series resistance 有权
标题翻译：用于控制等效串联电阻的电容器设计
公开(公告)号：US20060139847A1
公开(公告)日：2006-06-29
申请号：US11024060
申请日：2004-12-28
申请人： Yuan-Liang Li , David Figueroa , Farzaneh Yahyaei-moayyed , Dong Zhong
发明人： Yuan-Liang Li , David Figueroa , Farzaneh Yahyaei-moayyed , Dong Zhong
IPC分类号： H01G4/228
CPC分类号： H01G4/012 , H01G4/232 , H01G4/30 , H01L2224/16 , H01L2924/15312 , H01L2924/19103 , H01L2924/19106 , H05K1/0231
摘要： According to some embodiments, a capacitor includes a first external capacitor plane comprising a first at least one terminal of a first polarity, and a first internal capacitor plane comprising a second at least one terminal of the first polarity. The second at least one terminal of the first polarity may be electrically coupled to the first at least one terminal of the first polarity, and a total area of the second at least one terminal of the first polarity may be less than a total area of the first at least one terminal of the first polarity.
摘要翻译：根据一些实施例，电容器包括包括第一极性的第一至少一个端子和包括第一极性的第二至少一个端子的第一内部电容器平面的第一外部电容器平面。第一极性的第二至少一个端子可以电耦合到第一极性的第一至少一个端子，并且第一极性的第二至少一个端子的总面积可以小于第一极性的总面积第一极性的至少一个端子。

4. 发明申请

US20060256502A1 CAPACITOR HAVING SEPARATE TERMINALS ON THREE OR MORE SIDES AND METHODS OF FABRICATION 审中-公开
标题翻译：在三面或三面以上具有单独端子的电容器和制造方法
公开(公告)号：US20060256502A1
公开(公告)日：2006-11-16
申请号：US11460290
申请日：2006-07-27
申请人： Yuan-Liang Li , David Figueroa , Chee-Yee Chung
发明人： Yuan-Liang Li , David Figueroa , Chee-Yee Chung
IPC分类号： H01G4/228
CPC分类号： H01G4/232
摘要： A multilayer capacitor comprises separate terminals on at least three sides, and on as many as six sides. The capacitor can be fabricated in a large number of different configurations, types, and sizes, depending upon the target application. The separate terminals that are disposed on different sides of the capacitor can be readily coupled to a variety of different adjacent conductors, such as die terminals (including bumpless terminals or bars), IC package terminals (including pads or bars), and the terminals of adjacent discrete components. Methods of fabrication, as well as application of the capacitor to an electronic assembly, are also described.
摘要翻译：多层电容器包括在至少三个侧面上以及多达六个侧面的分开的端子。根据目标应用，电容器可以以大量不同的配置，类型和尺寸制造。设置在电容器的不同侧上的单独的端子可以容易地耦合到各种不同的相邻导体，例如模具端子（包括无扰动端子或条），IC封装端子（包括焊盘或条），以及端子相邻的分立元件。还描述了制造方法以及将电容器应用于电子组件。

5. 发明申请

US20050156280A1 Integrated circuit packages with sandwiched capacitors 有权
标题翻译：具有夹层电容器的集成电路封装
公开(公告)号：US20050156280A1
公开(公告)日：2005-07-21
申请号：US11080126
申请日：2005-03-15
申请人： P. R. Patel , Chee-Yee Chung , David Figueroa , Robert Sankman , Yuan-Liang Li , Hong Xie , William Pinelin
发明人： P. R. Patel , Chee-Yee Chung , David Figueroa , Robert Sankman , Yuan-Liang Li , Hong Xie , William Pinelin
IPC分类号： H01L21/60 , H01L23/50 , H01L29/00
CPC分类号： H01L24/81 , H01L23/50 , H01L2224/16225 , H01L2224/16265 , H01L2224/81801 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10253 , H01L2924/14 , H01L2924/15311 , H01L2924/19041 , H01L2924/19103 , H01L2924/19104 , H01L2924/30105 , H01L2924/30107 , H01L2924/00
摘要： To provide high-speed, low inductance capacitive decoupling, an integrated circuit (IC) package includes capacitors positioned within the mounting region between a die and an IC package substrate. A variety of types and sizes of capacitors and substrates can be employed in a variety of geometrical arrangements. In some embodiments, capacitors are sandwiched between die terminals or bumps and the substrate conductors or pads, while in other embodiments, capacitors are positioned between bar-type conductors on the surface of the IC package substrate. Methods of fabrication, as well as application of the package to an electronic assembly and to an electronic system, are also described.
摘要翻译：为了提供高速，低电感电容去耦，集成电路（IC）封装包括位于管芯和IC封装衬底之间的安装区域内的电容器。各种类型和尺寸的电容器和基板可以用于各种几何布置。在一些实施例中，电容器夹在裸片端子或凸起之间以及衬底导体或衬垫之间，而在其它实施例中，电容器位于IC封装衬底的表面上的棒状导体之间。还描述了制造方法以及将包装应用于电子组件和电子系统。

6. 发明授权

US08468366B2 Method for securely storing a programmable identifier in a communication station 有权
标题翻译：用于在通信站中安全地存储可编程标识符的方法
公开(公告)号：US08468366B2
公开(公告)日：2013-06-18
申请号：US12054318
申请日：2008-03-24
申请人： David Figueroa , James A. Hutchison
发明人： David Figueroa , James A. Hutchison
IPC分类号： G06F21/00
CPC分类号： H04W12/12 , H04L63/0428 , H04L63/10
摘要： Disclosed is a method for storing an identifier in a first station having a secure non-volatile data store protected by cryptographic data, an identifier flag for indicating that the identifier has been written to the secure data store, and an authenticated trust agent that prohibits writing of an identifier to the secure data store if the identifier flag is set. In the method, the identifier is written to the secure non-volatile data store, wherein the identifier written to the secure data store is encrypted using the cryptographic data. The identifier flag is irreversibly set after writing the identifier to the secure data store so that the trust agent prohibits another write of an identifier to the secure data store.
摘要翻译：公开了一种用于在具有由密码数据保护的安全非易失性数据存储器的第一站中存储标识符的方法，用于指示标识符已被写入安全数据存储器的标识符标志以及禁止写入的认证信任代理的标识符到安全数据存储器，如果设置了标识符标志。在该方法中，将标识符写入安全非易失性数据存储器，其中使用密码数据对写入安全数据存储器的标识符进行加密。在将标识符写入安全数据存储器之后，标识符标志被不可逆地设置，使得信任代理禁止对安全数据存储器另外写入标识符。

7. 发明申请

US20070002519A1 High ESR low ESL capacitor 有权
公开(公告)号：US20070002519A1
公开(公告)日：2007-01-04
申请号：US11174063
申请日：2005-06-30
申请人： Yuan-Liang Li , David Figueroa , Nicholas Holmberg
发明人： Yuan-Liang Li , David Figueroa , Nicholas Holmberg
IPC分类号： H01G4/005
CPC分类号： H01G4/255 , H01G4/30 , Y10T29/435
摘要： In some embodiments, a capacitor includes a first conductive layer electrically coupled to a first terminal, a second conductive layer electrically coupled to a second terminal, a floated conductive layer disposed between the first and second conductive layers, and a plurality of non-conductive layers respectively disposed between each of the conductive layers. Other embodiments are disclosed and claimed.

8. 发明申请

US20060091564A1 System to control effective series resistance of decoupling capacitor 有权
标题翻译：系统来控制去耦电容的有效串联电阻
公开(公告)号：US20060091564A1
公开(公告)日：2006-05-04
申请号：US10976716
申请日：2004-10-29
申请人： Dong Zhong , David Figueroa , Yuan-Liang Li , Michael Desmith
发明人： Dong Zhong , David Figueroa , Yuan-Liang Li , Michael Desmith
IPC分类号： H01L23/52 , H01L23/48
CPC分类号： H01L23/50 , H01L2224/16225 , H01L2924/01079 , H01L2924/15311 , H01L2924/15312 , H01L2924/19106
摘要： According to some embodiments, a system includes an integrated circuit package to support an integrated circuit die. The integrated circuit package may include a plurality of conductive contacts and a decoupling capacitor. The decoupling capacitor may include a positive terminal contact pad coupled to a first one of the plurality of conductive contacts, the positive terminal contact pad comprising a first substantially non-conductive area, and a negative terminal contact pad coupled to a second one of the plurality of conductive contacts, the negative terminal contact pad comprising a second substantially non-conductive area.
摘要翻译：根据一些实施例，系统包括用于支撑集成电路管芯的集成电路封装。集成电路封装可以包括多个导电触点和去耦电容器。去耦电容器可以包括耦合到多个导电触点中的第一个的正极端子接触焊盘，正极端子接触焊盘包括第一基本上不导电的区域，以及耦合到多个导电触点中的第二个的负极端子接触焊盘的导电触点，负极接触焊盘包括第二基本上不导电的区域。

9. 发明申请

US20060261465A1 CIRCUIT BOARD WITH TRACE CONFIGURATION FOR HIGH-SPEED DIGITAL DIFFERENTIAL SIGNALING 失效
标题翻译：具有高速数字差分信号的跟踪配置的电路板
公开(公告)号：US20060261465A1
公开(公告)日：2006-11-23
申请号：US11459951
申请日：2006-07-26
申请人： Yuan-Liang Li , Jiangqi He , Dong Zhong , David Figueroa
发明人： Yuan-Liang Li , Jiangqi He , Dong Zhong , David Figueroa
IPC分类号： H01L23/12
CPC分类号： H01P3/081 , H01L23/49822 , H01L23/49838 , H01L23/66 , H01L2223/6627 , H01L2924/0002 , H01L2924/1903 , H05K1/0242 , H05K1/0245 , H05K1/0265 , H05K3/4644 , H05K2201/0715 , H05K2201/09236 , H05K2201/09672 , H05K2201/0979 , H05K2201/098 , H05K2203/0733 , H01L2924/00
摘要： Trace configurations for carrying high-speed digital differential signals provide for reduced conduction loss and improved signal integrity. In one embodiment, a circuit board has a first set of conductive traces disposed on non-conductive material, and a second set of conductive traces parallel to the first set and disposed within the conductive material. The second set is separated from the first set by non-conductive material. Corresponding traces of the first and second sets may be in a stacked configuration. In other embodiments, conductive material may be provided between corresponding traces of the first and second sets resulting in an “I-shaped” or “U-shaped” cross-section. In yet other embodiments, the trace configurations have “T-shaped” and “L-shaped” cross-sections.
摘要翻译：用于承载高速数字差分信号的跟踪配置提供了降低的传导损耗和改善的信号完整性。在一个实施例中，电路板具有设置在非导电材料上的第一组导电迹线和平行于第一组并设置在导电材料内的第二组导电迹线。第二组与非导电材料与第一组分离。第一组和第二组的相应迹线可以是堆叠配置。在其他实施例中，导电材料可以设置在第一组和第二组的相应迹线之间，导致“I形”或“U形”横截面。在其它实施例中，迹线构造具有“T形”和“L形”横截面。

10. 发明申请

US20050029555A1 Silicon building blocks in integrated circuit packaging 有权
标题翻译：集成电路封装中的硅积木
公开(公告)号：US20050029555A1
公开(公告)日：2005-02-10
申请号：US10931497
申请日：2004-08-31
申请人： David Figueroa , Dong Zhong , Yuan-Liang Li , Jiangqi He , Cengiz Palanduz
发明人： David Figueroa , Dong Zhong , Yuan-Liang Li , Jiangqi He , Cengiz Palanduz
IPC分类号： H01L23/48 , H01L23/498 , H01L27/148
CPC分类号： H01L23/49827 , H01L23/481 , H01L2224/16 , H01L2924/00014 , H01L2924/01019 , H01L2924/3011 , H01L2224/0401
摘要： An improved silicon building block is disclosed. In an embodiment, the silicon building block has at least two vias through it. The silicon building block is doped and the vias filled with a first material, and, optionally, selected ones of the vias filled instead with a second material. In an alternative embodiment, regions of the silicon building block have metal deposited on them.
摘要翻译：公开了一种改进的硅结构单元。在一个实施例中，硅结构块具有通过其的至少两个通孔。硅结构单元被掺杂，并且通孔填充有第一材料，并且可选地，填充了选定的通孔，而不是用第二材料填充。在替代实施例中，硅积层的区域具有沉积在其上的金属。

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