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1. 发明授权

US5659794A System architecture for improved network input/output processing 失效
标题翻译：用于改进网络输入/输出处理的系统架构
公开(公告)号：US5659794A
公开(公告)日：1997-08-19
申请号：US414900
申请日：1995-03-31
申请人： Charles R. Caldarale , Peter J. Hancock , David R. Johnson , Robert M. Malek , James R. McBreen , Hans C. Mikkelsen , Jerome J. Witalka
发明人： Charles R. Caldarale , Peter J. Hancock , David R. Johnson , Robert M. Malek , James R. McBreen , Hans C. Mikkelsen , Jerome J. Witalka
IPC分类号： H04L12/56 , H04L29/06 , H04L29/08 , H01J3/00
CPC分类号： H04L29/06 , H04L69/32
摘要： A network input/output processing system for sending and receiving messages between a large scale computer system and associated communications networks. Executive operating system services provide access to a control table, an input queue, and an output queue stored in the computer system's main memory. A network input/output processor responds to requests by application programs, through a communications program, for receiving input from and sending output to a network, concurrently with requests to communicate with directly attached peripheral devices such as disk drives, tape drives, and printers. The network input/output processor receives initialization, reset, and termination requests via the control table. Requests to receive input are received from the input queue. Input data is stored into buffers as directed by the input request. Requests to send output are received from the output queue. Output data is read from the buffers as directed by the output request. Executive operating system services provide for control of input data transfers and output data transfers. Special purpose Instruction Processor instructions provide the capability to build control programs for processing input and output messages used by the network input/output processor to effect message transfers, thereby minimizing host instruction pathlength for communications I/O. The system architecture minimizes internal data copy between processes by using transferable buffers as communications buffers.
摘要翻译：一种用于在大规模计算机系统和相关联的通信网络之间发送和接收消息的网络输入/输出处理系统。执行操作系统服务提供对存储在计算机系统的主存储器中的控制表，输入队列和输出队列的访问。网络输入/输出处理器通过通信程序响应于应用程序的请求，用于从与网络接收的输入和向网络发送输出，以及与直接连接的外围设备（例如磁盘驱动器，磁带驱动器和打印机）进行通信的请求同时进行。网络输入/输出处理器通过控制表接收初始化，复位和终止请求。从输入队列接收到接收输入的请求。输入数据按输入请求的指示存储到缓冲区中。从输出队列接收请求发送输出。按照输出请求的指示从缓冲区读取输出数据。执行操作系统服务提供对输入数据传输和输出数据传输的控制。特殊用途指令处理器指令提供构建控制程序的能力，用于处理网络输入/输出处理器使用的输入和输出消息，以实现消息传输，从而最小化通信I / O的主机指令路径长度。系统架构通过使用可传输缓冲区作为通信缓冲区来最小化进程之间的内部数据复制。

2. 发明授权

US4437157A Dynamic subchannel allocation 失效
标题翻译：动态子通道分配
公开(公告)号：US4437157A
公开(公告)日：1984-03-13
申请号：US255585
申请日：1981-04-20
申请人： Jerome J. Witalka , Duane G. Kurth , David J. Baber
发明人： Jerome J. Witalka , Duane G. Kurth , David J. Baber
IPC分类号： G06F13/12 , G06F3/00 , G06F3/04
CPC分类号： G06F13/122
摘要： An apparatus for and a method of Dynamic Subchannel Allocation permitting easily field modifiable assignment of Input/Output (I/O) subchannels to I/O channels. Many present day medium-to-large scale computers have an I/O unit(s) with a fixed number of I/O ports or I/O channels for the transmission of information between the computer and peripheral devices. Improvements to these I/O channels, now common in the art, permit multiple peripheral devices to be coupled to the computer through a single I/O channel. Each of these multiple peripheral devices may be said to communicate through an I/O subchannel. A given I/O subchannel designation logically specifies the hardware within the shared I/O channel that is dedicated to communication with the corresponding one of the multiple peripheral devices coupled to that shared I/O channel. The present invention is an improvement which provides for allocation of I/O subchannels to I/O channels in the field rather than at time of manufacture. A random access memory (RAM) is employed which provides the correlation between each I/O subchannel and the I/O channel to which it has been allocated. The RAM is called the Channel Descriptor Stack (CDS). The CDS may be loaded using a variety of techniques. In the preferred embodiment, the CDS is loaded via a specialized processor, called a system support processor (SSP), which also performs those tasks normally associated with system control (e.g., system reconfiguration, interface to the system operator, casualty recovery, etc.).
摘要翻译：一种用于动态子信道分配的装置和方法，其允许将输入/输出（I / O）子信道容易地现场修改为I / O通道。许多现在的中型到大型计算机具有I / O单元，其具有固定数量的I / O端口或I / O通道，用于在计算机和外围设备之间传输信息。这些现有技术中常见的这些I / O通道的改进允许多个外围设备通过单个I / O通道耦合到计算机。这些多个外围设备中的每一个可以被称为通过I / O子信道进行通信。给定的I / O子信道指定逻辑地指定专用于与耦合到该共享I / O通道的多个外围设备中的对应的一个通信的共享I / O通道内的硬件。本发明是一种改进，其提供了在现场的I / O信道中分配I / O子信道，而不是在制造时。使用随机存取存储器（RAM），其提供每个I / O子信道与其已被分配到的I / O信道之间的相关性。 RAM称为通道描述符堆栈（CDS）。 CDS可以使用各种技术加载。在优选实施例中，CDS通过专门的处理器（称为系统支持处理器（SSP））来加载，该处理器也执行通常与系统控制相关的那些任务（例如，系统重新配置，与系统操作员的接口，伤员恢复等））。

3. 发明授权

US4511967A Simultaneous load and verify of a device control store from a support processor via a scan loop 失效
标题翻译：通过扫描循环从支持处理器同时加载和验证设备控制存储
公开(公告)号：US4511967A
公开(公告)日：1985-04-16
申请号：US466761
申请日：1983-02-15
申请人： Jerome J. Witalka , Howard L. Buettner , James G. Ellsworth
发明人： Jerome J. Witalka , Howard L. Buettner , James G. Ellsworth
IPC分类号： G01R31/3185 , G06F11/273 , G06F1/00
CPC分类号： G01R31/318547 , G01R31/318566 , G06F11/2294
摘要： The loading (writing) of plural successive data strings of specifiable bit-length and numbers to a scan/set testable register (called a CONTROL STORE SCAN LOOP STRING) from which it may then be transferred to a control store (called a CONTROL STORE (RAM)) both within a remote slave digital logic device (called a CENTRAL COMPLEX) is bit-serially conducted upon one signal line of a scan/set network by a controlling digital logic device (called a SUPPORT PROCESSOR) in substantially simultaneous time to the reading of the previous contents of such register (and control store) bit-serially via another signal line of said scan/set network. Both signal lines and devices together form a circular BIT-SERIAL SCAN LOOP, upon which the bit-serial writing and reading is time overlapped. The data strings read are the echo-back of the data strings previously written, and are, in a first operational mode called ECHO, lodged in a buffer memory (called a SCAN/SET BUFFER) of the controlling digital logic device wherein, subsequent to communication, they may be programmably compared with the data strings written in verification of process integrity. In a selectable alternative second operational mode called VERIFY, each successive data string read back is, in substantially simultaneous time, automatically compared with the data string as previously written. Thusly, loading (writing) and reading and verifying activities on variably specifiable numbers of data strings of variably specifiable bit-length communicated upon a BIT-SERIAL SCAN LOOP all transpire substantially concurrently in simultaneous time.
摘要翻译：将可指定位长和数字的多个连续数据串加载（写入）到扫描/设置可测试寄存器（称为控制存储扫描循环字符串），然后将其从传输到控制存储器（称为CONTROL STORE RAM））在远程从属数字逻辑器件（称为CENTRAL COMPLEX）中，通过控制数字逻辑器件（称为支持处理器）在扫描/设置网络的一个信号线上进行位串行传输通过所述扫描/设置网络的另一个信号线来顺序读取这种寄存器（和控制存储器）的先前内容。两个信号线和器件一起形成一个圆形的BIT串行扫描环，位串行写入和读取时间重叠。读取的数据串是先前写入的数据串的回波，并且被称为ECHO的第一操作模式存储在控制数字逻辑器件的缓冲存储器（称为SCAN / SET BUFFER）中，其中，在通信，它们可以可编程地与在验证过程完整性中编写的数据串进行比较。在称为VERIFY的可选择的备选的第二操作模式中，读取的每个连续的数据串在大致同时的时间内与先前写过的数据串自动地进行比较。因此，在双向串行扫描环路上通信的可变指定位长度的可变指定数量的数据串的加载（写入）和读取和验证活动全部同时在同时发生。

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