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1. 发明授权

US07572557B2 Non-collinear end-to-end structures with sub-resolution assist features 失效
标题翻译：具有次分辨率辅助功能的非共线端对端结构
公开(公告)号：US07572557B2
公开(公告)日：2009-08-11
申请号：US11297209
申请日：2005-12-07
申请人： Charles H. Wallace , Shannon E. Daviess , Swaminathan Sivakumar
发明人： Charles H. Wallace , Shannon E. Daviess , Swaminathan Sivakumar
IPC分类号： G03F1/00 , H01L21/00 , G06F17/50
CPC分类号： G03F1/36
摘要： Sub-resolution assist features for non-collinear features are described for use in photolithography. A photolithography mask with elongated features is synthesized. An end-to-end gap between two features if found for which the ends of the two features facing the gap are linearly offset from one another. A sub-resolution assist feature is applied to the end-to-end gap between the elongated features, and the synthesized photolithography mask is modified to include the sub-resolution assist feature.
摘要翻译：描述了非共线特征的子分辨率辅助功能，用于光刻。合成具有细长特征的光刻掩模。如果发现两个特征面对间隙的两端的端部彼此线性偏移，则两个特征之间的端对端间隙。子分辨率辅助特征被应用于细长特征之间的端到端间隙，并且合成的光刻掩模被修改为包括子分辨率辅助特征。

2. 发明授权

US07521157B2 Cross-shaped sub-resolution assist feature 失效
标题翻译：十字形分解辅助功能
公开(公告)号：US07521157B2
公开(公告)日：2009-04-21
申请号：US11351084
申请日：2006-02-09
申请人： Charles H. Wallace , Swaminathan Sivakumar , Shannon E. Daviess
发明人： Charles H. Wallace , Swaminathan Sivakumar , Shannon E. Daviess
IPC分类号： G03F1/00
CPC分类号： G03F1/36
摘要： Cross-shaped sub-resolution assist features may be utilized to print lithographic patterns in semiconductor fabrication processes. The crosses may be isolated structures or may be part of a grid arrangement. The main features, such as contacts, may be positioned on the mask so as to be intersected by the cross-shaped sub-resolution assist features. In some embodiments, the cross-shaped sub-resolution assist features may intersect the main feature at its center point in both the x and y directions.
摘要翻译：在半导体制造工艺中可以使用十字形分解辅助特征来印刷平版印刷图案。十字架可以是隔离结构，也可以是网格布置的一部分。诸如触点的主要特征可以位于掩模上，以便与十字形分解辅助特征相交。在一些实施例中，十字形辅助分辨率辅助特征可以在x和y方向的中心点处与主要特征相交。

3. 发明申请

US20130320456A1 GATE ALIGNED CONTACT AND METHOD TO FABRICATE SAME 有权
标题翻译：门对齐接触件和方法制作
公开(公告)号：US20130320456A1
公开(公告)日：2013-12-05
申请号：US13995678
申请日：2011-12-22
申请人： Oleg Golonzka , Swaminathan Sivakumar , Charles H. Wallace , Tahir Ghani
发明人： Oleg Golonzka , Swaminathan Sivakumar , Charles H. Wallace , Tahir Ghani
IPC分类号： H01L21/28 , H01L27/085
CPC分类号： H01L21/76897 , H01L21/28008 , H01L21/30625 , H01L21/32 , H01L21/76805 , H01L21/823431 , H01L21/823437 , H01L21/823468 , H01L21/823475 , H01L21/823481 , H01L23/535 , H01L27/0207 , H01L27/088 , H01L27/0886 , H01L29/0653 , H01L29/66545
摘要： Gate aligned contacts and methods of forming gate aligned contacts are described. For example, a method of fabricating a semiconductor structure includes forming a plurality of gate structures above an active region formed above a substrate. The gate structures each include a gate dielectric layer, a gate electrode, and sidewall spacers. A plurality of contact plugs is formed, each contact plug formed directly between the sidewall spacers of two adjacent gate structures of the plurality of gate structures. A plurality of contacts is formed, each contact formed directly between the sidewall spacers of two adjacent gate structures of the plurality of gate structures. The plurality of contacts and the plurality of gate structures are formed subsequent to forming the plurality of contact plugs.
摘要翻译：描述门对齐的触点和形成栅极对准触点的方法。例如，制造半导体结构的方法包括在形成在衬底上方的有源区上方形成多个栅极结构。栅极结构各自包括栅极介电层，栅电极和侧壁间隔物。形成多个接触插塞，每个接触插塞直接形成在多个门结构的两个相邻门结构的侧壁间隔件之间。形成多个触点，每个触点直接形成在多个栅极结构的两个相邻栅极结构的侧壁间隔件之间。在形成多个接触插塞之后形成多个触点和多个栅极结构。

4. 发明申请

US20090267175A1 DOUBLE PATTERNING TECHNIQUES AND STRUCTURES 有权
标题翻译：双重图案技术和结构
公开(公告)号：US20090267175A1
公开(公告)日：2009-10-29
申请号：US12111702
申请日：2008-04-29
申请人： Charles H. Wallace , Matthew Tingey , Swaminathan Sivakumar
发明人： Charles H. Wallace , Matthew Tingey , Swaminathan Sivakumar
IPC分类号： H01L21/308 , H01L27/00
CPC分类号： H01L21/308 , H01L21/0271 , H01L21/3086 , H01L21/3088
摘要： Double patterning techniques and structures are generally described. In one example, a method includes depositing a first photoresist to a semiconductor substrate, forming a first integrated circuit (IC) pattern in the first photoresist, the first IC pattern comprising one or more trench structures, protecting the first IC pattern in the first photoresist from actions that form a second IC pattern in a second photoresist, depositing the second photoresist to the first IC pattern, and forming the second IC pattern in the second photoresist, the second IC pattern comprising one or more structures that are sufficiently close to the one or more trench structures of the first IC pattern to cause scumming of the second photoresist in the one or more trench structures of the first IC pattern.
摘要翻译：通常描述双重图案形成技术和结构。在一个实例中，一种方法包括将第一光致抗蚀剂沉积到半导体衬底，在第一光致抗蚀剂中形成第一集成电路（IC）图案，第一IC图案包括一个或多个沟槽结构，保护第一光致抗蚀剂中的第一IC图案从在第二光致抗蚀剂中形成第二IC图案的动作，将第二光致抗蚀剂沉积到第一IC图案，以及在第二光致抗蚀剂中形成第二IC图案，第二IC图案包括一个或多个足够接近该一个的结构或更多个沟槽结构，以使第一IC图案的一个或多个沟槽结构中的第二光致抗蚀剂浮渣。

5. 发明申请

US20140017899A1 DOUBLE PATTERNING LITHOGRAPHY TECHNIQUES 有权
标题翻译：双重图案平铺技术
公开(公告)号：US20140017899A1
公开(公告)日：2014-01-16
申请号：US13976090
申请日：2011-12-29
申请人： Charles H. Wallace , Swaminathan Sivakumar , Matthew L. Tingey , Chanaka D. Munasinghe , Nadia M. Rahhal-Orabi
发明人： Charles H. Wallace , Swaminathan Sivakumar , Matthew L. Tingey , Chanaka D. Munasinghe , Nadia M. Rahhal-Orabi
IPC分类号： H01L21/308
CPC分类号： H01L21/3088 , H01L21/0337
摘要： Techniques are disclosed for double patterning of a lithographic feature using a barrier layer between the pattern layers. In some cases, the techniques may be implemented with double patterning of a one- or two-dimensional photolithographic feature, for example. In some embodiments, the barrier layer is deposited to protect a first photoresist pattern prior to application of a second photoresist pattern thereon and/or to tailor (e.g., shrink) one or more of the critical dimensions of a trench, hole, or other etchable geometric feature to be formed in a substrate or other suitable surface via lithographic processes. In some embodiments, the techniques may be implemented to generate/print small features (e.g., less than or equal to about 100 nm) including one- and two-dimensional features/structures of varying complexity.
摘要翻译：公开了使用图案层之间的阻挡层对光刻特征进行双重图案化的技术。在一些情况下，例如，可以通过双图案化一维或二维光刻特征来实现这些技术。在一些实施例中，沉积阻挡层以在施加第二光致抗蚀剂图案之前保护第一光致抗蚀剂图案和/或定制（例如，收缩）沟槽，孔或其它可蚀刻的一个或多个临界尺寸通过光刻工艺在衬底或其它合适的表面中形成的几何特征。在一些实施例中，可以实施技术来生成/打印包括不同复杂度的一维和二维特征/结构的小特征（例如，小于或等于约100nm）。

6. 发明申请

US20090001431A1 Method for forming semiconductor contacts 失效
标题翻译：半导体触点形成方法
公开(公告)号：US20090001431A1
公开(公告)日：2009-01-01
申请号：US11821971
申请日：2007-06-26
申请人： Nadia Rahhal-Orabi , Charles H. Wallace , Alison Davis , Swaminathan Sivakumar
发明人： Nadia Rahhal-Orabi , Charles H. Wallace , Alison Davis , Swaminathan Sivakumar
IPC分类号： H01L29/78 , H01L21/4763
CPC分类号： H01L21/76804 , H01L21/76816 , H01L29/78
摘要： In one embodiment of the invention, contact patterning may be divided into two or more passes which may allow designers to control the gate height critical dimension relatively independent from the contact top critical dimension.
摘要翻译：在本发明的一个实施例中，接触图案化可以被分成两个或更多遍，这可以允许设计者相对独立于接触顶部临界尺寸来控制栅极高度临界尺寸。

7. 发明授权

US10211088B2 Self-aligned isotropic etch of pre-formed vias and plugs for back end of line (BEOL) interconnects 有权
公开(公告)号：US10211088B2
公开(公告)日：2019-02-19
申请号：US15743616
申请日：2015-09-10
申请人： INTEL CORPORATION , Charles H. Wallace , Swaminathan Sivakumar
发明人： Charles H. Wallace , Elliot N. Tan , Paul A. Nyhus , Swaminathan Sivakumar
IPC分类号： H01L21/768 , H01L23/522 , H01L21/311 , H01L23/528 , H01L21/033
摘要： Self-aligned isotropic etch processes for via and plug patterning for back end of line (BEOL) interconnects, and the resulting structures, are described. In an example, a method of fabricating an interconnect structure for an integrated circuit includes removing a sacrificial or permanent placeholder material of a subset of a plurality of holes or trenches through openings in a patterning layer. The method also includes removing the patterning layer and filling the subset of the plurality of holes or trenches with a permanent material.

8. 发明授权

US09716037B2 Gate aligned contact and method to fabricate same 有权
公开(公告)号：US09716037B2
公开(公告)日：2017-07-25
申请号：US13995678
申请日：2011-12-22
申请人： Oleg Golonzka , Swaminathan Sivakumar , Charles H. Wallace , Tahir Ghani
发明人： Oleg Golonzka , Swaminathan Sivakumar , Charles H. Wallace , Tahir Ghani
IPC分类号： H01L21/768 , H01L27/088 , H01L21/306 , H01L27/02 , H01L21/8234 , H01L21/28 , H01L29/66
CPC分类号： H01L21/76897 , H01L21/28008 , H01L21/30625 , H01L21/32 , H01L21/76805 , H01L21/823431 , H01L21/823437 , H01L21/823468 , H01L21/823475 , H01L21/823481 , H01L23/535 , H01L27/0207 , H01L27/088 , H01L27/0886 , H01L29/0653 , H01L29/66545
摘要： Gate aligned contacts and methods of forming gate aligned contacts are described. For example, a method of fabricating a semiconductor structure includes forming a plurality of gate structures above an active region formed above a substrate. The gate structures each include a gate dielectric layer, a gate electrode, and sidewall spacers. A plurality of contact plugs is formed, each contact plug formed directly between the sidewall spacers of two adjacent gate structures of the plurality of gate structures. A plurality of contacts is formed, each contact formed directly between the sidewall spacers of two adjacent gate structures of the plurality of gate structures. The plurality of contacts and the plurality of gate structures are formed subsequent to forming the plurality of contact plugs.

9. 发明授权

US07915171B2 Double patterning techniques and structures 有权
标题翻译：双重图案化技术和结构
公开(公告)号：US07915171B2
公开(公告)日：2011-03-29
申请号：US12111702
申请日：2008-04-29
申请人： Charles H. Wallace , Matthew Tingey , Swaminathan Sivakumar
发明人： Charles H. Wallace , Matthew Tingey , Swaminathan Sivakumar
IPC分类号： H01L21/306 , G03F1/00
CPC分类号： H01L21/308 , H01L21/0271 , H01L21/3086 , H01L21/3088
摘要： Double patterning techniques and structures are generally described. In one example, a method includes depositing a first photoresist to a semiconductor substrate, forming a first integrated circuit (IC) pattern in the first photoresist, the first IC pattern comprising one or more trench structures, protecting the first IC pattern in the first photoresist from actions that form a second IC pattern in a second photoresist, depositing the second photoresist to the first IC pattern, and forming the second IC pattern in the second photoresist, the second IC pattern comprising one or more structures that are sufficiently close to the one or more trench structures of the first IC pattern to cause scumming of the second photoresist in the one or more trench structures of the first IC pattern.
摘要翻译：通常描述双重图案形成技术和结构。在一个实例中，一种方法包括将第一光致抗蚀剂沉积到半导体衬底，在第一光致抗蚀剂中形成第一集成电路（IC）图案，第一IC图案包括一个或多个沟槽结构，保护第一光致抗蚀剂从在第二光致抗蚀剂中形成第二IC图案的动作，将第二光致抗蚀剂沉积到第一IC图案，以及在第二光致抗蚀剂中形成第二IC图案，第二IC图案包括一个或多个足够接近该一个的结构或更多个沟槽结构，以使第一IC图案的一个或多个沟槽结构中的第二光致抗蚀剂浮渣。

10. 发明授权

US07709866B2 Method for forming semiconductor contacts 失效
标题翻译：半导体触点形成方法
公开(公告)号：US07709866B2
公开(公告)日：2010-05-04
申请号：US11821971
申请日：2007-06-26
申请人： Nadia Rahhal-Orabi , Charles H. Wallace , Alison Davis , Swaminathan Sivakumar
发明人： Nadia Rahhal-Orabi , Charles H. Wallace , Alison Davis , Swaminathan Sivakumar
IPC分类号： H01L29/51 , H01L21/469
CPC分类号： H01L21/76804 , H01L21/76816 , H01L29/78
摘要： In one embodiment of the invention, contact patterning may be divided into two or more passes which may allow designers to control the gate height critical dimension relatively independent from the contact top critical dimension.
摘要翻译：在本发明的一个实施例中，接触图案化可以被分成两个或更多遍，这可以允许设计者相对独立于接触顶部临界尺寸来控制栅极高度临界尺寸。

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