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1. 发明申请

US20080282128A1 Method of Error Correction Code on Solid State Disk to Gain Data Security and Higher Performance 审中-公开
标题翻译：固态盘上纠错码的方法可以获得数据安全性和更高的性能
公开(公告)号：US20080282128A1
公开(公告)日：2008-11-13
申请号：US11932461
申请日：2007-10-31
申请人： Charles Chung Lee , David Queichang Chow , Abraham Chih-Kang Ma , I-Kang Yu , Ming-Shiang Shen
发明人： Charles Chung Lee , David Queichang Chow , Abraham Chih-Kang Ma , I-Kang Yu , Ming-Shiang Shen
IPC分类号： H03M13/07 , G06F11/10 , H03M13/21
CPC分类号： G06F11/1068
摘要： An electronic data storage device having a Reed Solomon (RS) decoder including a syndrome calculator block responsive to information including data and overhead and operative to generate a syndrome, in accordance with an embodiment of the present invention. The electronic data storage device further includes a root finder block coupled to receive said syndrome and operative to generate at least two roots, said RS decoder for processing said two roots to generate at least one error address identifying a location in said data wherein said error lies; and an erasure syndrome calculator block responsive to said information and operative to generate an erasure syndrome, said RS decoder responsive to said information identifying a disk crash, said RS decoder for processing said erasure syndrome to generate an erasure error to recover the data in said disk crash.
摘要翻译：一种具有Reed Solomon（RS）解码器的电子数据存储装置，其包括响应于包括数据和开销的信息并且可操作以产生综合征的校正子计算器块，其根据本发明的实施例。该电子数据存储装置还包括一个根取景器块，它被耦合以接收所述校正子并且可操作以产生至少两个根，所述RS解码器用于处理所述两个根以产生标识所述数据中的位置的至少一个错误地址，其中所述误差位于 ; 以及响应于所述信息并且可操作地产生擦除综合征的擦除错误计算器块，所述RS解码器响应于所述识别盘崩溃的信息，所述RS解码器用于处理所述擦除综合征以产生擦除错误以恢复所述盘中的数据崩溃

2. 发明授权

US07680977B2 Page and block management algorithm for NAND flash 有权
标题翻译： NAND闪存的页面和块管理算法
公开(公告)号：US07680977B2
公开(公告)日：2010-03-16
申请号：US11779804
申请日：2007-07-18
申请人： Jianjun Luo , Chris Tsu , Charles Chung Lee , David Queichang Chow
发明人： Jianjun Luo , Chris Tsu , Charles Chung Lee , David Queichang Chow
IPC分类号： G06F12/00
CPC分类号： G06F12/0246 , G06F12/0292 , G06F13/28 , G06F2212/1036 , G06F2212/7211
摘要： A flash controller is adapted to communicate with a host and the flash memory and including volatile memory configured to store a page-block table of logical addresses addressable by the physical addresses. The logical addresses are used by the controller to identify the blocks. The table has an address mapping table and a property value table, the property value table includes property values, each of the property values being increased in value every time a block is written up to a maximum value and being associated with a block of a predetermined group of blocks and indicative of the number of times a block has been written, the property values corresponding to the logical addresses of the address mapping table, wherein the maximum number the property values of the predetermined group of blocks take on is adjustably different than the maximum number the property values of another group of blocks.
摘要翻译：闪存控制器适于与主机和闪存进行通信，并且包括被配置为存储可通过物理地址寻址的逻辑地址的页块表的易失性存储器。逻辑地址由控制器用于识别块。该表具有地址映射表和属性值表，属性值表包括属性值，每当一个块写入最大值并且与预定的块相关联时，每个属性值都被增加，指示块的写入次数的一组块，对应于地址映射表的逻辑地址的属性值，其中预定块组的属性值的最大数量可以与最大数量的另一组块的属性值。

3. 发明授权

US07818492B2 Source and shadow wear-leveling method and apparatus 失效
标题翻译：源和阴影磨损均衡方法和装置
公开(公告)号：US07818492B2
公开(公告)日：2010-10-19
申请号：US11767417
申请日：2007-06-22
申请人： Jianjun Luo , Chris Tsu , Charles Chung Lee , David Queichang Chow
发明人： Jianjun Luo , Chris Tsu , Charles Chung Lee , David Queichang Chow
IPC分类号： G06F13/00
CPC分类号： G06F13/28 , G06F12/0246 , G06F12/0292 , G06F2212/1036 , G06F2212/7211
摘要： A flash memory system includes flash memory organized into a plurality of blocks of pages for storage of information, a page including data and spare, the blocks being identifiable, within the flash memory, by a physical address. The system further has a flash controller for communicating with a host and the flash memory and includes volatile memory for storing a source-shadow table of logical addresses identifying blocks addressable by the physical addresses. The source-shadow table has an address mapping table and a property value table. The property value table is used to store property values, each of which is associated with a block of a predetermined group of blocks and is indicative of the number of times a block has been written since the last erase operation performed thereon. The property values correspond to the logical addresses of the address mapping table, wherein a block having been written no more than two times is re-written to different areas of the flash memory without requiring an erase operation.
摘要翻译：闪速存储器系统包括组织成多个页面块的闪存，用于存储信息，包括数据和备用的页面，所述块可被闪存存储器内的物理地址识别。该系统还具有用于与主机和闪速存储器进行通信的闪存控制器，并且包括用于存储识别通过物理地址可寻址的块的逻辑地址的源影子表的易失性存储器。 source-shadow表有一个地址映射表和一个属性值表。属性值表用于存储属性值，每个属性值与预定块块组相关联，并且表示自上次执行的上次擦除操作以来写入块的次数。属性值对应于地址映射表的逻辑地址，其中已经写入不超过两次的块被重写到闪速存储器的不同区域，而不需要擦除操作。

4. 发明授权

US07769944B2 Partial-write-collector algorithm for multi level cell (MLC) flash 有权
标题翻译：用于多级单元（MLC）闪存的部分写入 - 收集器算法
公开(公告)号：US07769944B2
公开(公告)日：2010-08-03
申请号：US11774906
申请日：2007-07-09
申请人： Jianjun Luo , Chris Tsu , Charles Chung Lee , David Queichang Chow
发明人： Jianjun Luo , Chris Tsu , Charles Chung Lee , David Queichang Chow
IPC分类号： G06F12/00
CPC分类号： G11C16/102 , G06F8/65 , G11C2211/5641
摘要： A flash memory system includes a multi level cell (MLC) flash memory organized into blocks and having pages of information, which has data and spare. The MLC flash memory includes at least a temporary area to store at least a portion of a page of information during a partial write operation. The MLC flash memory stores a page of information into a block identified by a target physical address. The flash memory system further includes a flash card micro-controller causes communication between a host flash card controller and the MLC flash memory and includes a buffer memory configured to store a portion of a page of information, where the micro-controller writes the at least a portion of a page of information to the temporary area and later copies the written at least a portion of a page of information into the block identified by a target physical address.
摘要翻译：闪存系统包括组织成块并具有数据和备用的信息页的多级单元（MLC）闪存。在部分写入操作期间，MLC闪速存储器至少包括用于存储信息页的至少一部分的临时区域。 MLC闪速存储器将一页信息存储到由目标物理地址识别的块中。闪存系统还包括闪存卡微控制器引起主机闪存卡控制器和MLC闪速存储器之间的通信，并且包括被配置为存储信息页的一部分的缓冲存储器，其中微控制器写入至少信息页面的一部分到临时区域，并且稍后将写入信息页的至少一部分复制到由目标物理地址识别的块中。

5. 发明申请

US20090055667A1 MEMORY CARD WITH POWER SAVING 有权
标题翻译：存储卡与省电
公开(公告)号：US20090055667A1
公开(公告)日：2009-02-26
申请号：US11841550
申请日：2007-08-20
申请人： Jianjun Luo , David Queichang Chow
发明人： Jianjun Luo , David Queichang Chow
IPC分类号： G06F1/32 , G06F1/04
CPC分类号： G06F1/3203 , G06F1/324 , G06F1/3275 , Y02D10/126 , Y02D10/14
摘要： A memory system includes power saving arbitrator responsive to a clock oscillator and having a first clock rate. The power saving arbitrator includes an active enable circuit responsive to a host clock and a host command and operative to generate an active enable signal for causing the power saving arbitrator to generate a core logic/memories signal having a second clock rate that is adjustably lower in rate than the first clock rate, said active enable circuit operative to detect the absence of a host command for a predetermined period of time and when the predetermined period of time exceeds a threshold value, the power saving arbitrator operative to reduce the second clock rate.
摘要翻译：存储器系统包括响应于时钟振荡器并具有第一时钟速率的节电仲裁器。省电仲裁器包括响应于主机时钟和主机命令的有效使能电路，并且可操作以产生有效使能信号，以使得省电仲裁器产生具有可调节地较低的第二时钟速率的核心逻辑/存储器信号所述有效使能电路可操作以在预定时间段内检测到主机命令的不存在，并且当所述预定时间段超过阈值时，所述节电仲裁器可操作地降低所述第二时钟速率。

6. 发明授权

US07895457B2 Memory card with power saving 有权
标题翻译：存储卡省电
公开(公告)号：US07895457B2
公开(公告)日：2011-02-22
申请号：US11841550
申请日：2007-08-20
申请人： Jianjun Luo , David Queichang Chow
发明人： Jianjun Luo , David Queichang Chow
IPC分类号： G06F1/00 , G06F1/32 , G06F12/00
CPC分类号： G06F1/3203 , G06F1/324 , G06F1/3275 , Y02D10/126 , Y02D10/14
摘要： A memory system includes power saving arbitrator responsive to a clock oscillator and having a first clock rate. The power saving arbitrator includes an active enable circuit responsive to a host clock and a host command and operative to generate an active enable signal for causing the power saving arbitrator to generate a core logic/memories signal having a second clock rate that is adjustably lower in rate than the first clock rate, said active enable circuit operative to detect the absence of a host command for a predetermined period of time and when the predetermined period of time exceeds a threshold value, the power saving arbitrator operative to reduce the second clock rate.
摘要翻译：存储器系统包括响应于时钟振荡器并具有第一时钟速率的节电仲裁器。省电仲裁器包括响应于主机时钟和主机命令的有效使能电路，并且可操作以产生有效使能信号，以使得省电仲裁器产生具有可调节地较低的第二时钟速率的核心逻辑/存储器信号所述有效使能电路可操作以在预定时间段内检测到主机命令的不存在，并且当所述预定时间段超过阈值时，所述节电仲裁器可操作地降低所述第二时钟速率。

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