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    • 1. 发明授权
      US5459742A Solid state disk memory using storage devices with defects 失效
    • Solid state disk memory using storage devices with defects
    • 使用存储设备的固态硬盘内存有缺陷
    • US5459742A
    • 1995-10-17
    • US212334
    • 1994-03-14
    • Charles Cassidy , Paul Kemp , Donald Smelser
    • Charles Cassidy , Paul Kemp , Donald Smelser
    • G06F11/10 , H03M13/15 , H03M13/00 , G06F11/00
    • G06F11/1044 , H03M13/152 , H03M13/1575 , H03M13/6575
    • A computer system includes a main memory that is able to make use of DRAM memory devices having a relatively high level of bad cells (hard faults). An EDC circuit is provided which uses combinatorial logic to perform a BCH code type of error detection and correction. A primary feature is the recognition that due to use of high density integrated circuits--gate arrays--it is no longer necessary to use sequential logic to decode the multiple-bit error correcting codes. An EDC with 128-bits of data and a check bit field 41-bits wide, using a BCH code, constructed in ASIC sea-of-gates technology using about 87,000 logic gates, can correct 5-bits in error and can detect 6-bits in error. By using multiple-bit EDC in the controller for main memory, it is no longer necessary that all DRAM devices be ostensibly "perfect." A certain density of non-functional memory cells can be tolerated, yet the memory system will still return perfect data. The added cost of multiple-bit EDC, including the added cost of extra storage for the check bits and the EDC circuit itself, is more than compensated by reduced cost of the DRAMs. In a addition the computer system includes a solid-state disk type memory for a computer system is able to make use of DRAM memory devices having a relatively high level of bad cells (hard faults). An EDC circuit is employed to perform a Reed-Solomon code type of error detection and correction. A primary feature is the recognition that it is no longer necessary that all DRAM devices be ostensibly "perfect." A certain density of non-functional memory cells can be tolerated, yet the memory system will still return perfect data. The added cost of multiple-bit EDC, including the added cost of extra storage for the check bits and the EDC circuit itself, is more than compensated by reduced cost of the DRAMs. A preferred data formatter circuit to convert between symbol and word data is also described.
    • 计算机系统包括能够利用具有相对较高级别的坏小区（硬故障）的DRAM存储器件的主存储器。 提供了一种EDC电路，其使用组合逻辑来执行BCH码类型的错误检测和校正。 主要特征是识别由于使用高密度集成电路 - 门阵列 - 不再需要使用顺序逻辑来解码多位纠错码。 具有128位数据的EDC和41位宽的校验位字段，使用使用约87,000个逻辑门的ASIC海底技术构建的BCH码可以校正错误的5位，并且可以检测6- 位错误。 通过在主存储器的控制器中使用多位EDC，不再需要所有DRAM器件表面上“完美”。 可以容忍一定密度的非功能性存储单元，但是存储器系统仍将返回完美的数据。 多位EDC的附加成本，包括用于校验位和EDC电路本身的额外存储的附加成本，通过降低DRAM的成本来补偿。 此外，计算机系统包括用于计算机系统的固态盘型存储器能够利用具有相对较高水平的坏小区（硬故障）的DRAM存储器件。 采用EDC电路来执行错误检测和校正的Reed-Solomon码类型。 一个主要特征就是认识到，不再需要所有的DRAM器件表面上都是“完美的”。 可以容忍一定密度的非功能性存储单元，但是存储器系统仍将返回完美的数据。 多位EDC的附加成本，包括用于校验位和EDC电路本身的额外存储的附加成本，通过降低DRAM的成本来补偿。 还描述了用于在符号和字数据之间转换的优选数据格式化电路。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 2. 发明授权
      US5343426A Data formater/converter for use with solid-state disk memory using storage devices with defects 失效
    • Data formater/converter for use with solid-state disk memory using storage devices with defects
    • US5343426A
    • 1994-08-30
    • US897164
    • 1992-06-11
    • Charles Cassidy , Paul Kemp
    • Charles Cassidy , Paul Kemp
    • G06F11/10 , G11C29/00 , H03M13/00
    • G06F11/1044 , G11C29/88
    • A computer system includes a main memory that is able to make use of DRAM memory devices having a relatively high level of bad cells (hard faults). An EDC circuit is provided which uses combinatorial logic to perform a BCH code type of error detection and correction. A primary feature is the recognition that due to use of high density integrated circuits--gate arrays--it is no longer necessary to use sequential logic to decode the multiple-bit error correcting codes. An EDC with 128-bits of data and a check bit field 41-bits wide, using a BCH code, constructed in ASIC sea-of-gates technology using about 87,000 logic gates, can correct 5-bits in error and can detect 6-bits in error. By using multiple-bit EDC in the controller for main memory, it is no longer necessary that all DRAM devices be ostensibly "perfect." A certain density of non-functional memory cells can be tolerated, yet the memory system will still return perfect data. The added cost of multiple-bit EDC, including the added cost of extra storage for the check bits and the EDC circuit itself, is more than compensated by reduced cost of the DRAMs. In a addition the computer system includes a solid-state disk type memory for a computer system is able to make use of DRAM memory devices having a relatively high level of bad cells (hard faults). An EDC circuit is employed to perform a Reed-Solomon code type of error detection and correction. A primary feature is the recognition that it is no longer necessary that all DRAM devices be ostensibly "perfect." A certain density of non-functional memory cells can be tolerated, yet the memory system will still return perfect data. The added cost of multiple-bit EDC, including the added cost of extra storage for the check bits and the EDC circuit itself, is more than compensated by reduced cost of the DRAMs. A preferred data formatter circuit to convert between symbol and word data is also described.
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
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