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    • 7. 发明授权
    • Tri-state output logic with zero quiescent current by one input control
    • 具有零静态电流的三态输出逻辑由一个输入控制
    • US07385422B2
    • 2008-06-10
    • US11217341
    • 2005-09-02
    • Shui-Mu LinChien-Sheng ChenNien-Hui KungDer-Jiunn WangJing-Meng LiuWei-Hsin Wei
    • Shui-Mu LinChien-Sheng ChenNien-Hui KungDer-Jiunn WangJing-Meng LiuWei-Hsin Wei
    • H03K19/02
    • G06F1/26
    • A voltage generating circuit, which generates tri-state logic output in accordance with high, low or floating of the input node, is proposed. The present voltage generating circuit includes: a pulse generating circuit for generating a plurality of pulses; a voltage selecting circuit having a pair of NMOS transistors coupled in common source, each drain of the NMOS transistors is coupled to a current source respectively, both gates of the NMOS transistors are coupled to an input node, and the paired drain of the NMOS transistors generate a pair of voltage output; a plurality of flip-flops, which couple to drains of the NMOS transistors to lock the voltage output of the NMOS transistors in accordance with the pulses; an inner voltage-generating unit couples to the input node for providing a floating voltage level; and a plurality of switches controlled by the pulses for controlling the normal operation of the voltage selecting circuit and the conduction between the inner-voltage generating unit with the input node.
    • 提出了根据输入节点的高,低或浮动产生三态逻辑输出的电压产生电路。 本电压发生电路包括:产生多个脉冲的脉冲发生电路; 一个电压选择电路,具有耦合在公共源极上的一对NMOS晶体管,NMOS晶体管的每个漏极分别耦合到电流源,NMOS晶体管的两个栅极耦合到输入节点,并且NMOS晶体管的成对漏极 产生一对电压输出; 多个触发器,其耦合到NMOS晶体管的漏极以根据脉冲锁定NMOS晶体管的电压输出; 内部电压产生单元耦合到输入节点以提供浮动电压电平; 以及由用于控制电压选择电路的正常操作的脉冲控制的多个开关以及内部电压产生单元与输入节点之间的导通。
    • 8. 发明申请
    • Tri-state output logic with zero quiescent current by one input control
    • 具有零静态电流的三态输出逻辑由一个输入控制
    • US20060279331A1
    • 2006-12-14
    • US11217341
    • 2005-09-02
    • Shui-Mu LinChien-Sheng ChenNien-Hui KungDer-Jiunn WangJing-Meng LiuWei-Hsin Wei
    • Shui-Mu LinChien-Sheng ChenNien-Hui KungDer-Jiunn WangJing-Meng LiuWei-Hsin Wei
    • H03K19/00
    • G06F1/26
    • A voltage generating circuit, which generates tri-state logic output in accordance with high, low or floating of the input node, is proposed. The present voltage generating circuit includes: a pulse generating circuit for generating a plurality of pulses; a voltage selecting circuit having a pair of NMOS transistors coupled in common source, each drain of the NMOS transistors is coupled to a current source respectively, both gates of the NMOS transistors are coupled to an input node, and the paired drain of the NMOS transistors generate a pair of voltage output; a plurality of flip-flops, which couple to drains of the NMOS transistors to lock the voltage output of the NMOS transistors in accordance with the pulses; an inner voltage-generating unit couples to the input node for providing a floating voltage level; and a plurality of switches controlled by the pulses for controlling the normal operation of the voltage selecting circuit and the conduction between the inner-voltage generating unit with the input node.
    • 提出了根据输入节点的高,低或浮动产生三态逻辑输出的电压产生电路。 本电压发生电路包括:产生多个脉冲的脉冲发生电路; 一个电压选择电路,具有耦合在公共源极上的一对NMOS晶体管,NMOS晶体管的每个漏极分别耦合到电流源,NMOS晶体管的两个栅极耦合到输入节点,并且NMOS晶体管的成对漏极 产生一对电压输出; 多个触发器,其耦合到NMOS晶体管的漏极以根据脉冲锁定NMOS晶体管的电压输出; 内部电压产生单元耦合到输入节点以提供浮动电压电平; 以及由用于控制电压选择电路的正常操作的脉冲控制的多个开关以及内部电压产生单元与输入节点之间的导通。
    • 9. 发明授权
    • Feed-forward method for improving a transient response for a DC—DC power conversion and DC—DC voltage converter utilizing the same
    • 用于改善DC-DC电力转换的瞬态响应的前馈方法和利用其的DC-DC电压转换器
    • US07026800B2
    • 2006-04-11
    • US10683395
    • 2003-10-14
    • Jing-Meng LiuLiang-Pin TaiDer-Jiunn Wang
    • Jing-Meng LiuLiang-Pin TaiDer-Jiunn Wang
    • G05F1/40H02M1/12
    • H02M3/156
    • In a method for a DC-DC power conversion performed by a switching mode buck voltage converter, the power conversion is split into two or more stages, and a feed-forward signal is generated by one of the stages and sent to another stage prior thereto. The feed-forward signal is generated by responding to a load current transient, such as output voltage drop, ON-duty increment or decrement occurred in the PWM control loop, error amp output swinging, and any other detectable signals in response to load current transient of the voltage converter. As a result, the performance of the DC-DC voltage converter is improved due to the prior stage modulated early in time, and both lower ripple current and peak current in steady state operations and fast response to load current transient conditions could be simultaneously obtained.
    • 在由开关模式降压电压转换器执行的DC-DC功率转换的方法中,功率转换被分为两级或更多级,并且前级信号由其中一级产生并发送到其之前的另一级 。 前馈信号通过响应负载电流瞬变而产生,例如输出电压降,PWM控制环中发生的占空比增量或减量,误差放大器输出摆幅以及响应于负载电流瞬变的任何其他可检测信号 的电压转换器。 结果,由于早期调制了DC-DC电压转换器的性能,可以同时获得稳态运行中的较低纹波电流和峰值电流以及对负载电流瞬态条件的快速响应。
    • 10. 发明授权
    • Display panel control circuit and multi-chip module thereof
    • 显示面板控制电路及其多芯片模块
    • US08836614B1
    • 2014-09-16
    • US13778543
    • 2013-02-27
    • Der-Jiunn Wang
    • Der-Jiunn Wang
    • G09G3/28H05B37/02
    • G09G3/3677
    • The present invention provides a display panel control circuit, including: a voltage adjustment unit including a high side switch coupled between an output terminal and a high voltage source, a low side switch coupled between the output terminal and a low voltage source, and a voltage adjustment switch coupled between the output terminal and a switching node; a direction control unit, including a first diode having a cathode coupled to the switching node and an anode coupled to a voltage rising node, and a second diode having an anode coupled the switching node and a cathode coupled to a voltage falling node; a voltage rising resistor coupled between the voltage rising node and a shaping voltage source; and a voltage falling resistor coupled between the voltage falling node and the shaping voltage source.
    • 本发明提供了一种显示面板控制电路,包括:电压调整单元,包括耦合在输出端子和高电压源之间的高侧开关,耦合在输出端子和低电压源之间的低侧开关,以及电压 耦合在输出端和交换节点之间的调节开关; 方向控制单元,包括具有耦合到所述开关节点的阴极的第一二极管和耦合到电压上升节点的阳极,以及耦合到所述开关节点的阳极和耦合到降压节点的阴极的第二二极管; 耦合在电压上升节点和整形电压源之间的升压电阻器; 以及耦合在电压下降节点和整形电压源之间的降压电阻器。