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    • 1. 发明授权
    • Data recovery system and the method thereof
    • 数据恢复系统及其方法
    • US07242735B2
    • 2007-07-10
    • US10632925
    • 2003-08-04
    • Chao-Hsin LuYi-Shu ChangShiu-Rong TongKuang-Hsi Hsieh
    • Chao-Hsin LuYi-Shu ChangShiu-Rong TongKuang-Hsi Hsieh
    • H04L7/02
    • H04L7/0338
    • A data recovery system and method is disclosed, which comprises an oversampler, a phase detection circuit, a data pick circuit, a data overlap/skip detection circuit and a data correction circuit. The oversampler oversamples an input signal and thus generates oversampled signals. The phase detection circuit receives for detecting transitions of the oversampled signals and outputting a phase signal. The data pick circuit receives the phase signal, accordingly groups the oversampled signals into n groups and picks one group as an output data. The data overlap/skip detection circuit determines if data is overlapped or skipped according to the phase signal and the last phase signal. The data correction circuit corrects data when data is overlapped or skipped and outputs an accurate output data.
    • 公开了一种数据恢复系统和方法,其包括过采样器,相位检测电路,数据拾取电路,数据重叠/跳过检测电路和数据校正电路。 过采样器过采样输入信号,从而产生过采样信号。 相位检测电路接收用于检测过采样信号的转变并输出相位信号。 数据采集​​电路接收相位信号,相应地将过采样信号分组为n组,并选择一组作为输出数据。 数据重叠/跳跃检测电路根据相位信号和最后的相位信号确定数据是否重叠或跳过。 当数据重叠或跳过时,数据校正电路校正数据,并输出准确的输出数据。
    • 5. 发明授权
    • Audio control device
    • 音频控制装置
    • US07194097B2
    • 2007-03-20
    • US10441045
    • 2003-05-20
    • Chu-Ting SuYi-Shu ChangJul-Cheng HuangWen-Chi Wang
    • Chu-Ting SuYi-Shu ChangJul-Cheng HuangWen-Chi Wang
    • H03F21/00
    • H03F3/68Y10T307/696
    • An Audio Codec which comprises a power selecting circuit an audio compiler circuit and a control amplifier circuit. The power selecting circuit receives at least a primary power source and an auxiliary power source and outputs a working power selected from the power sources. The auxiliary power source is selected and output to the control amplifier circuit only when the computer is at a power-off status. When the computer is power-on, the primary power source will be selected and output to both the audio compiler circuit and the control amplifier circuit. Therefore, the Audio Codec of the present invention only needs one set of internally furnished control amplifier circuit to both operate on the normal power-on status and perform the Power OFF CD function.
    • 音频编解码器,其包括音频编译器电路和控制放大器电路的功率选择电路。 功率选择电路至少接收主电源和辅助电源,并输出从电源选择的工作电源。 只有当计算机处于断电状态时,辅助电源被选择并输出到控制放大器电路。 当计算机上电时,主电源将被选择并输出到音频编译器电路和控制放大器电路。 因此,本发明的音频编解码器仅需要一套内部布置的控制放大器电路,以在正常的开机状态下操作并执行断电CD功能。
    • 6. 发明授权
    • Multi-jack detector
    • 多插孔检测器
    • US07071702B2
    • 2006-07-04
    • US10776536
    • 2004-02-12
    • Ming-Jane HsiehChuting SuYi-Shu ChangMing-Lih Lin
    • Ming-Jane HsiehChuting SuYi-Shu ChangMing-Lih Lin
    • G01R31/04G01R19/00H01H31/02H04M1/00
    • H04R5/04H04B1/20H04R29/00H04R2420/05
    • A multi-jack detector for detecting states of a plurality of jacks. Each jack comprises a first switch having a first normally closed terminal and a first output terminal. The multi-jack detector comprises a plurality of bias resistors each coupled to one of the first output terminals, respectively; a control unit for determining the states of the plurality of jacks; wherein the first normally closed terminals are commonly coupled to a first node and the control unit determines the states of the plurality of jacks according to a voltage at the first node. Because the voltage at the first node is different for each state of the jacks, the detector can detects the states of the jacks using a single I/O pin.
    • 一种用于检测多个插孔的状态的多插孔检测器。 每个插孔包括具有第一常闭端子和第一输出端子的第一开关。 多插座检测器包括分别耦合到第一输出端之一的多个偏置电阻器; 用于确定所述多个插孔的状态的控制单元; 其中所述第一常闭端子共同耦合到第一节点,并且所述控制单元根据所述第一节点处的电压来确定所述多个插孔的状态。 因为第一节点处的电压对于插孔的每个状态是不同的,所以检测器可以使用单个I / O引脚来检测插座的状态。
    • 10. 发明授权
    • Phase swallow device and signal generator using the same
    • 相位吞咽装置和信号发生器使用相同
    • US07084687B2
    • 2006-08-01
    • US10896118
    • 2004-07-22
    • Wen-Shiung WengMing-Chun ChangChi-Kung KuanYi-Shu ChangKuo-Lin Tai
    • Wen-Shiung WengMing-Chun ChangChi-Kung KuanYi-Shu ChangKuo-Lin Tai
    • G06F1/04
    • G06F1/10H03L7/00
    • A signal generator for generating a clock with lower jitter. The signal generator includes a multi-phase clock generator for generating a plurality of multi-phase reference clocks with same frequency, a multiplexer for selecting one reference clock as an output clock according to a phase selecting signal, a phase-swallow control unit having a comparator for comparing a swallow value with a reference value out of order and outputting the comparing result as a swallow control signal, and a clock selector for receiving the swallow control signal and generating the phase selecting signal. Because the reference value is provided by a counter in bit-reversed, the swallow control signal is dispersed smoothly and the jitter of the output clock is reduced.
    • 用于产生具有较低抖动的时钟的信号发生器。 信号发生器包括用于产生具有相同频率的多个多相参考时钟的多相时钟发生器,用于根据相位选择信号选择一个参考时钟作为输出时钟的多路复用器,具有相位选择信号的相位控制单元 比较器,用于将吞咽值与参考值进行比较,并输出比较结果作为吞咽控制信号;以及时钟选择器,用于接收吞咽控制信号并产生相位选择信号。 由于参考值由位反转的计数器提供,所以吞咽控制信号平滑地分散,并且输出时钟的抖动减小。