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1. 发明授权

US08850276B2 Systems and methods for efficient data shuffling in a data processing system 有权
标题翻译：数据处理系统中高效数据刷新的系统和方法
公开(公告)号：US08850276B2
公开(公告)日：2014-09-30
申请号：US13239683
申请日：2011-09-22
申请人： Changyou Xu , Zongwang Li , Sancar K. Olcay , Yang Han , Kaichi Zhang
发明人： Changyou Xu , Zongwang Li , Sancar K. Olcay , Yang Han , Kaichi Zhang
IPC分类号： G06F11/00 , G11C29/00 , H03M13/27 , H03M13/00 , H04L1/00 , H03M13/41 , H03M13/11 , H03M13/39
CPC分类号： H04L1/0052 , H03M13/1102 , H03M13/271 , H03M13/3905 , H03M13/41 , H03M13/6561 , H04L1/0071
摘要： Various embodiments of the present invention provide systems and methods for data processing. Such data processing includes data shuffling.
摘要翻译：本发明的各种实施例提供了用于数据处理的系统和方法。这样的数据处理包括数据混洗。

2. 发明申请

US20130080844A1 Systems and Methods for Efficient Data Shuffling in a Data Processing System 有权
标题翻译：数据处理系统中有效数据刷新的系统和方法
公开(公告)号：US20130080844A1
公开(公告)日：2013-03-28
申请号：US13239683
申请日：2011-09-22
申请人： Changyou Xu , Zongwang Li , Sancar K. Olcay , Yang Han , Kaichi Zhang
发明人： Changyou Xu , Zongwang Li , Sancar K. Olcay , Yang Han , Kaichi Zhang
IPC分类号： G06F11/10 , G06F12/00
CPC分类号： H04L1/0052 , H03M13/1102 , H03M13/271 , H03M13/3905 , H03M13/41 , H03M13/6561 , H04L1/0071
摘要： Various embodiments of the present invention provide systems and methods for data processing. For example, a method for data processing is disclosed that includes: receiving a data input having at least a first local chunk and a second local chunk, the data input also being defined as having at least a first global chunk and a second global chunk; rearranging an order of the first local chunk and the second local chunk to yield a locally interleaved data set; storing the locally interleaved data set to a first memory, such that the first global chunk is stored to a first memory space, and the second global chunk is stored to a second memory space; accessing the locally interleaved data set from the first memory; and storing the locally interleaved data set to a second memory. The first global chunk is stored to a third memory space defined at least in part based on the first memory space, and the second global chunk is stored to a fourth memory space defined at least in part based on the second memory space.
摘要翻译：本发明的各种实施例提供了用于数据处理的系统和方法。例如，公开了一种用于数据处理的方法，包括：接收具有至少第一本地块和第二本地块的数据输入，所述数据输入还被定义为具有至少第一全局块和第二全局块; 重新排列第一本地块和第二本地块的顺序以产生本地交织的数据集; 将本地交织的数据集存储到第一存储器，使得第一全局块被存储到第一存储器空间，并且第二全局块被存储到第二存储器空间; 从所述第一存储器访问本地交错数据集; 以及将本地交织的数据集存储到第二存储器。第一全局块被存储到基于第一存储器空间至少部分地定义的第三存储器空间，并且第二全局块被存储到基于第二存储器空间至少部分地定义的第四存储器空间。

3. 发明申请

US20120331363A1 Systems and Methods for Reduced Format Non-Binary Decoding 有权
标题翻译：减少格式非二进制解码的系统和方法
公开(公告)号：US20120331363A1
公开(公告)日：2012-12-27
申请号：US13167771
申请日：2011-06-24
申请人： Zongwang Li , Wu Chang , Chung-Li Wang , Changyou Xu , Shaohua Yang , Yang Han
发明人： Zongwang Li , Wu Chang , Chung-Li Wang , Changyou Xu , Shaohua Yang , Yang Han
IPC分类号： G06F11/07
CPC分类号： H03M13/1171 , H03M13/27 , H03M13/3723 , H03M13/612
摘要： Various embodiments of the present invention provide systems and methods for data processing. As an example, a data processing circuit is disclosed that includes a data detecting circuit having: a first vector translation circuit, a second vector translation circuit, and a data detector core circuit. The data detecting circuit is operable to receive an input data set and at least one input vector in a first format. The at least one input vector corresponds to a portion of the input data set. The first vector translation circuit is operable to translate the at least one vector to a second format. The data detector core circuit is operable to apply a data detection algorithm to the input data set and the at least one vector in the second format to yield a detected output. The second vector translation circuit operable to translate a derivative of the detected output to the first format to yield an output vector.
摘要翻译：本发明的各种实施例提供了用于数据处理的系统和方法。作为示例，公开了一种数据处理电路，其包括具有第一向量转换电路，第二向量转换电路和数据检测器核心电路的数据检测电路。数据检测电路可操作以接收第一格式的输入数据集和至少一个输入向量。至少一个输入向量对应于输入数据集的一部分。第一向量翻译电路可操作以将至少一个向量转换为第二格式。数据检测器核心电路可操作以将数据检测算法应用于输入数据集和第二格式的至少一个向量以产生检测到的输出。第二向量转换电路可操作以将检测到的输出的导数转换为第一格式以产生输出向量。

4. 发明授权

US08947804B2 Systems and methods for combined binary and non-binary data processing 有权
标题翻译：用于组合二进制和非二进制数据处理的系统和方法
公开(公告)号：US08947804B2
公开(公告)日：2015-02-03
申请号：US13316758
申请日：2011-12-12
申请人： Zongwang Li , Chung-Li Wang , Shaohua Yang , Changyou Xu , Lei Chen , Yang Han
发明人： Zongwang Li , Chung-Li Wang , Shaohua Yang , Changyou Xu , Lei Chen , Yang Han
IPC分类号： G11B5/02 , H03M13/11
CPC分类号： G11B5/02 , H03M13/1171
摘要： Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing system is disclosed that includes a combination data decoder circuit. The combination data decoder circuit includes: a non-binary data decoder circuit and a binary data decoder circuit.
摘要翻译：本发明的各种实施例提供了用于数据处理的系统和方法。例如，公开了一种包括组合数据解码器电路的数据处理系统。组合数据解码器电路包括：非二进制数据解码器电路和二进制数据解码器电路。

5. 发明授权

US08560929B2 Systems and methods for non-binary decoding 有权
标题翻译：用于非二进制解码的系统和方法
公开(公告)号：US08560929B2
公开(公告)日：2013-10-15
申请号：US13167764
申请日：2011-06-24
申请人： Zongwang Li , Wu Chang , Chung-Li Wang , Changyou Xu , Shaohua Yang , Yang Han
发明人： Zongwang Li , Wu Chang , Chung-Li Wang , Changyou Xu , Shaohua Yang , Yang Han
IPC分类号： H03M13/00
CPC分类号： H04L1/0047 , H03M13/1171 , H03M13/134 , H03M13/255
摘要： Various embodiments of the present invention provide systems and methods for data processing. A data processing circuit is disclosed that includes: a data detector circuit, a first symbol constrained arrangement circuit, and a second symbol constrained arrangement circuit. The data detector circuit is operable to apply a data detection algorithm to a combination of a first input data set and a decoded data set to yield a detected output that includes a number of non-binary symbols. The first symbol constrained arrangement circuit is operable to receive the detected output and to re-arrange the detected output in accordance with a first arrangement algorithm to yield a re-arranged output. The bits for at least one non-binary symbol from the detected output are maintained together in the re-arranged output. The second symbol constrained arrangement circuit is operable to receive a second input data set and to re-arrange the second data input in accordance with a second arrangement algorithm to yield the decoded data set. The bits for at least one non-binary symbol from the second input data set are maintained together in the decoded data set output.
摘要翻译：本发明的各种实施例提供了用于数据处理的系统和方法。公开了一种数据处理电路，其包括：数据检测器电路，第一符号约束布置电路和第二符号约束布置电路。数据检测器电路可操作以将数据检测算法应用于第一输入数据集合和解码数据集合的组合，以产生包括多个非二进制符号的检测输出。第一符号约束布置电路可操作以接收检测到的输出并根据第一布置算法重新布置检测的输出以产生重新排列的输出。来自检测到的输出的至少一个非二进制符号的位在重新布置的输出中保持在一起。第二符号约束布置电路可操作以接收第二输入数据集并且根据第二布置算法重排第二数据输入以产生解码数据集。用于来自第二输入数据集的至少一个非二进制符号的位在解码数据集输出中一起保持。

6. 发明申请

US20120331370A1 Systems and Methods for Non-Binary Decoding 有权
标题翻译：非二进制解码的系统和方法
公开(公告)号：US20120331370A1
公开(公告)日：2012-12-27
申请号：US13167764
申请日：2011-06-24
申请人： Zongwang Li , Wu Chang , Chung-Li Wang , Changyou Xu , Shaohua Yang , Yang Han
发明人： Zongwang Li , Wu Chang , Chung-Li Wang , Changyou Xu , Shaohua Yang , Yang Han
IPC分类号： G06F11/08
CPC分类号： H04L1/0047 , H03M13/1171 , H03M13/134 , H03M13/255
摘要： Various embodiments of the present invention provide systems and methods for data processing. A data processing circuit is disclosed that includes: a data detector circuit, a first symbol constrained arrangement circuit, and a second symbol constrained arrangement circuit. The data detector circuit is operable to apply a data detection algorithm to a combination of a first input data set and a decoded data set to yield a detected output that includes a number of non-binary symbols. The first symbol constrained arrangement circuit is operable to receive the detected output and to re-arrange the detected output in accordance with a first arrangement algorithm to yield a re-arranged output. The bits for at least one non-binary symbol from the detected output are maintained together in the re-arranged output. The second symbol constrained arrangement circuit is operable to receive a second input data set and to re-arrange the second data input in accordance with a second arrangement algorithm to yield the decoded data set. The bits for at least one non-binary symbol from the second input data set are maintained together in the decoded data set output.
摘要翻译：本发明的各种实施例提供了用于数据处理的系统和方法。公开了一种数据处理电路，其包括：数据检测器电路，第一符号约束布置电路和第二符号约束布置电路。数据检测器电路可操作以将数据检测算法应用于第一输入数据集合和解码数据集合的组合，以产生包括多个非二进制符号的检测输出。第一符号约束布置电路可操作以接收检测到的输出并根据第一布置算法重新布置检测的输出以产生重新排列的输出。来自检测到的输出的至少一个非二进制符号的位在重新布置的输出中保持在一起。第二符号约束排列电路可操作以接收第二输入数据集并且根据第二布置算法重新布置第二数据输入以产生解码的数据集。用于来自第二输入数据集的至少一个非二进制符号的位在解码数据集输出中一起保持。

7. 发明授权

US08499231B2 Systems and methods for reduced format non-binary decoding 有权
标题翻译：缩减格式非二进制解码的系统和方法
公开(公告)号：US08499231B2
公开(公告)日：2013-07-30
申请号：US13167771
申请日：2011-06-24
申请人： Zongwang Li , Wu Chang , Chung-Li Wang , Changyou Xu , Shaohua Yang , Yang Han
发明人： Zongwang Li , Wu Chang , Chung-Li Wang , Changyou Xu , Shaohua Yang , Yang Han
IPC分类号： G06F11/00 , H03M13/00
CPC分类号： H03M13/1171 , H03M13/27 , H03M13/3723 , H03M13/612
摘要： Various embodiments of the present invention provide systems and methods for data processing. As an example, a data processing circuit is disclosed that includes a data detecting circuit having: a first vector translation circuit, a second vector translation circuit, and a data detector core circuit. The data detecting circuit is operable to receive an input data set and at least one input vector in a first format. The at least one input vector corresponds to a portion of the input data set. The first vector translation circuit is operable to translate the at least one vector to a second format. The data detector core circuit is operable to apply a data detection algorithm to the input data set and the at least one vector in the second format to yield a detected output. The second vector translation circuit operable to translate a derivative of the detected output to the first format to yield an output vector.
摘要翻译：本发明的各种实施例提供了用于数据处理的系统和方法。作为示例，公开了一种数据处理电路，其包括具有第一向量转换电路，第二向量转换电路和数据检测器核心电路的数据检测电路。数据检测电路可操作以接收第一格式的输入数据集和至少一个输入向量。至少一个输入向量对应于输入数据集的一部分。第一向量翻译电路可操作以将至少一个向量转换为第二格式。数据检测器核心电路可操作以将数据检测算法应用于输入数据集和第二格式的至少一个向量以产生检测到的输出。第二向量转换电路可操作以将检测到的输出的导数转换为第一格式以产生输出向量。

8. 发明申请

US20130339827A1 Adaptive Calibration of Noise Predictive Finite Impulse Response Filter 有权
标题翻译：噪声预测有限脉冲响应滤波器的自适应校准
公开(公告)号：US20130339827A1
公开(公告)日：2013-12-19
申请号：US13525182
申请日：2012-06-15
申请人： Yang Han , Shaohua Yang , Fan Zhang , Zongwang Li , Changyou Xu
发明人： Yang Han , Shaohua Yang , Fan Zhang , Zongwang Li , Changyou Xu
IPC分类号： G06F11/07
CPC分类号： G11B20/10046 , H03M13/1111 , H03M13/2957 , H03M13/6325 , H03M13/6343 , H04L25/03171 , H04L25/03318 , H04L25/067
摘要： Various embodiments of the present inventions are related to adaptive calibration of NPFIR filters in a data detector. For example, an apparatus for calibrating a noise predictive filter is disclosed, including a data detector operable to generate detected values for data sectors and having an embedded noise predictive finite impulse response filter. The apparatus also includes a comparator operable to determine whether a quality metric for a current one of the data sectors meets a noise threshold. The apparatus also includes a filter calibration circuit operable to adapt a number of filter coefficients for the noise predictive finite impulse response filter based on the detected values for the data sectors, and to omit the detected values for the current one of the data sectors from adaptation for one of the filter coefficients if the quality metric for the current one of the data sectors does not meet the noise threshold.
摘要翻译：本发明的各种实施例涉及数据检测器中的NPFIR滤波器的自适应校准。例如，公开了一种用于校准噪声预测滤波器的装置，包括可操作以产生数据扇区的检测值并具有嵌入式噪声预测有限脉冲响应滤波器的数据检测器。该装置还包括比较器，可操作以确定当前数据扇区的质量度量是否符合噪声阈值。该装置还包括滤波器校准电路，其可操作以基于用于数据扇区的检测值来适应用于噪声预测有限脉冲响应滤波器的多个滤波器系数，并且从适配中省去当前数据扇区的检测值对于当前一个数据扇区的质量度量不满足噪声阈值的滤波器系数之一。

9. 发明授权

US08719682B2 Adaptive calibration of noise predictive finite impulse response filter 有权
标题翻译：噪声预测有限脉冲响应滤波器的自适应校准
公开(公告)号：US08719682B2
公开(公告)日：2014-05-06
申请号：US13525182
申请日：2012-06-15
申请人： Yang Han , Shaohua Yang , Fan Zhang , Zongwang Li , Changyou Xu
发明人： Yang Han , Shaohua Yang , Fan Zhang , Zongwang Li , Changyou Xu
IPC分类号： G06F11/07
CPC分类号： G11B20/10046 , H03M13/1111 , H03M13/2957 , H03M13/6325 , H03M13/6343 , H04L25/03171 , H04L25/03318 , H04L25/067
摘要： Various embodiments of the present inventions are related to adaptive calibration of NPFIR filters in a data detector. For example, an apparatus for calibrating a noise predictive filter is disclosed, including a data detector operable to generate detected values for data sectors and having an embedded noise predictive finite impulse response filter. The apparatus also includes a comparator operable to determine whether a quality metric for a current one of the data sectors meets a noise threshold. The apparatus also includes a filter calibration circuit operable to adapt a number of filter coefficients for the noise predictive finite impulse response filter based on the detected values for the data sectors, and to omit the detected values for the current one of the data sectors from adaptation for one of the filter coefficients if the quality metric for the current one of the data sectors does not meet the noise threshold.
摘要翻译：本发明的各种实施例涉及数据检测器中的NPFIR滤波器的自适应校准。例如，公开了一种用于校准噪声预测滤波器的装置，包括可操作以产生数据扇区的检测值并具有嵌入式噪声预测有限脉冲响应滤波器的数据检测器。该装置还包括比较器，可操作以确定当前数据扇区的质量度量是否符合噪声阈值。该装置还包括滤波器校准电路，其可操作以基于用于数据扇区的检测值来适应用于噪声预测有限脉冲响应滤波器的多个滤波器系数，并且从适配中省去当前数据扇区的检测值对于当前一个数据扇区的质量度量不满足噪声阈值的滤波器系数之一。

10. 发明申请

US20130148232A1 Systems and Methods for Combined Binary and Non-Binary Data Processing 有权
标题翻译：组合二进制和非二进制数据处理的系统和方法
公开(公告)号：US20130148232A1
公开(公告)日：2013-06-13
申请号：US13316758
申请日：2011-12-12
申请人： Zongwang Li , Chung-Li Wang , Shaohua Yang , Changyou Xu , Lei Chen , Yang Han
发明人： Zongwang Li , Chung-Li Wang , Shaohua Yang , Changyou Xu , Lei Chen , Yang Han
IPC分类号： G11B5/035 , H03M7/00
CPC分类号： G11B5/02 , H03M13/1171
摘要： Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing system is disclosed that includes a combination data decoder circuit. The combination data decoder circuit includes: a non-binary data decoder circuit and a binary data decoder circuit.
摘要翻译：本发明的各种实施例提供了用于数据处理的系统和方法。例如，公开了包括组合数据解码器电路的数据处理系统。组合数据解码器电路包括：非二进制数据解码器电路和二进制数据解码器电路。

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