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1. 发明申请

US20120104484A1 NONVOLATILE MEMORY DEVICE AND MANUFACTURING METHOD THEREOF 有权
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US20120104484A1
公开(公告)日：2012-05-03
申请号：US13279708
申请日：2011-10-24
申请人： Changhyun LEE , Sung-II Chang , Byoungkeun Son
发明人： Changhyun LEE , Sung-II Chang , Byoungkeun Son
IPC分类号： H01L29/792
CPC分类号： H01L27/11582 , H01L29/792 , H01L45/1233 , H01L45/1253
摘要： A nonvolatile memory device includes a substrate, a stacked structure with conductive materials and first insulating materials and the conductive materials and the first insulating materials are alternately stacked on the substrate, and a plurality of pillars in contact with the substrate and the pillars extend through the stacked structure in a direction perpendicular to the substrate. The device also includes information storage layers between the conductive materials and the first insulating materials, and second insulating materials between the first insulating materials and the pillars.
摘要翻译：非易失性存储器件包括基板，具有导电材料和第一绝缘材料的堆叠结构，并且导电材料和第一绝缘材料交替地堆叠在基板上，并且与基板和支柱接触的多个支柱延伸穿过在垂直于衬底的方向上堆叠结构。该装置还包括在导电材料和第一绝缘材料之间的信息存储层，以及在第一绝缘材料和支柱之间的第二绝缘材料。

2. 发明申请

US20170186769A1 SEMICONDUCTOR DEVICE INCLUDING A STACK HAVING A SIDEWALL WITH RECESSED AND PROTRUDING PORTIONS 审中-公开
公开(公告)号：US20170186769A1
公开(公告)日：2017-06-29
申请号：US15456841
申请日：2017-03-13
申请人： Byoungkeun SON , Yoocheol SHIN , Changhyun LEE , Hyunjung KIM , Chung-II HYUN
发明人： Byoungkeun SON , Yoocheol SHIN , Changhyun LEE , Hyunjung KIM , Chung-II HYUN
IPC分类号： H01L27/11582 , H01L21/28 , H01L27/1157 , H01L27/11565
CPC分类号： H01L27/11582 , H01L21/28282 , H01L27/11519 , H01L27/11524 , H01L27/11556 , H01L27/11565 , H01L27/1157
摘要： A semiconductor device includes a substrate, a stack, and channel structures penetrating the stack. The stack includes gate electrodes and insulating layers alternately and repeatedly stacked on the substrate, and extending in a first direction. The channel structures in a first row are spaced apart from each other in the first direction. The stack includes a first sidewall that includes first recessed portions and first protruding portions. Each of first recessed portions is defined by an adjacent pair of the first recessed portions. Each of the first recessed portions has a shape recessed toward a first region of the stack between an adjacent pair of the channel structures of the first row. Each of the first recessed portions has a width that decreases in a direction toward the first region when measured along the first direction.

3. 发明申请

US20130140623A1 THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：三维半导体存储器件
公开(公告)号：US20130140623A1
公开(公告)日：2013-06-06
申请号：US13757273
申请日：2013-02-01
申请人： Changhyun LEE , ByoungKeun Son , Youngwoo Park
发明人： Changhyun LEE , ByoungKeun Son , Youngwoo Park
IPC分类号： H01L29/792
CPC分类号： H01L29/788 , H01L27/11551 , H01L27/11556 , H01L27/11578 , H01L29/04 , H01L29/7889 , H01L29/792 , H01L29/7926
摘要： A three-dimensional semiconductor memory device may include gap-fill insulating layers extending upward from a substrate, an electrode structure delimited by sidewalls of the gap-fill insulating layers, vertical structures provided between adjacent ones of the gap-fill insulating layers to penetrate the electrode structure, and at least one separation pattern extending along the gap-fill insulating layers and penetrating at least a portion of the electrode structure. The separation pattern may include at least one separation semiconductor layer.
摘要翻译：三维半导体存储器件可以包括从衬底向上延伸的间隙填充绝缘层，由间隙填充绝缘层的侧壁限定的电极结构，设置在相邻的间隙填充绝缘层之间的垂直结构以穿透电极结构，以及沿间隙填充绝缘层延伸并穿透电极结构的至少一部分的至少一个分离图案。分离图案可以包括至少一个分离半导体层。

4. 发明申请

US20150348983A1 SEMICONDUCTOR DEVICE INCLUDING A STACK HAVING A SIDEWALL WITH RECESSED AND PROTRUDING PORTIONS 有权
标题翻译：半导体器件，包括具有接收和引导部分的平台的堆叠
公开(公告)号：US20150348983A1
公开(公告)日：2015-12-03
申请号：US14724952
申请日：2015-05-29
申请人： Byoungkeun SON , Yoocheol SHIN , Changhyun LEE , Hyunjung KIM , Chung-II HYUN
发明人： Byoungkeun SON , Yoocheol SHIN , Changhyun LEE , Hyunjung KIM , Chung-II HYUN
IPC分类号： H01L27/115 , H01L29/423 , H01L29/788
CPC分类号： H01L27/11582 , H01L21/28282 , H01L27/11519 , H01L27/11524 , H01L27/11556 , H01L27/11565 , H01L27/1157
摘要： A semiconductor device includes a substrate, a stack, and channel structures penetrating the stack. The stack includes gate electrodes and insulating layers alternately and repeatedly stacked on the substrate, and extending in a first direction. The channel structures in a first row are spaced apart from each other in the first direction. The stack includes a first sidewall that includes first recessed portions and first protruding portions. Each of first recessed portions is defined by an adjacent pair of the first recessed portions. Each of the first recessed portions has a shape recessed toward a first region of the stack between an adjacent pair of the channel structures of the first row. Each of the first recessed portions has a width that decreases in a direction toward the first region when measured along the first direction.
摘要翻译：半导体器件包括衬底，堆叠和穿透堆叠的沟道结构。叠层包括交替重复层叠在基板上并沿第一方向延伸的栅电极和绝缘层。第一行中的通道结构在第一方向上彼此间隔开。堆叠包括第一侧壁，其包括第一凹部和第一突出部。每个第一凹部由相邻的一对第一凹部限定。每个第一凹部具有朝向第一排的相邻的一对通道结构之间的堆叠的第一区域凹陷的形状。每个第一凹部具有沿着第一方向测量时在朝向第一区域的方向上减小的宽度。

5. 发明申请

US20120112264A1 THREE-DIMENSIONAL SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME 有权
标题翻译：三维半导体器件及其制造方法
公开(公告)号：US20120112264A1
公开(公告)日：2012-05-10
申请号：US13290425
申请日：2011-11-07
申请人： Changhyun LEE , Chanjin Park , Byoungkeun Son , Sung-Il Chang
发明人： Changhyun LEE , Chanjin Park , Byoungkeun Son , Sung-Il Chang
IPC分类号： H01L29/792 , H01L27/06
CPC分类号： H01L27/11582 , H01L27/11551 , H01L27/11556 , H01L27/11578 , H01L29/0649 , H01L29/7926
摘要： A three-dimensional semiconductor device includes an upper structure on a lower structure, the upper structure including conductive patterns, a semiconductor pattern connected to the lower structure through the upper structure, and an insulating spacer between the semiconductor pattern and the upper structure, a bottom surface of the insulating spacer being positioned at a vertical level equivalent to or higher than an uppermost surface of the lower structure.
摘要翻译：三维半导体器件包括下结构的上结构，上结构包括导电图案，通过上结构连接到下结构的半导体图案，以及半导体图案和上结构之间的绝缘间隔物，底部绝缘间隔物的表面位于等于或高于下部结构的最上表面的垂直水平。

6. 发明申请

US20120098051A1 NONVOLATILE MEMORY DEVICE AND METHOD OF FORMING THE SAME 有权
标题翻译：非易失性存储器件及其形成方法
公开(公告)号：US20120098051A1
公开(公告)日：2012-04-26
申请号：US13281612
申请日：2011-10-26
申请人： Byoungkeun SON , Changhyun LEE , Jaegoo LEE , Kwang Soo SEOL , Byungkwan YOU
发明人： Byoungkeun SON , Changhyun LEE , Jaegoo LEE , Kwang Soo SEOL , Byungkwan YOU
IPC分类号： H01L29/78
CPC分类号： H01L29/66833 , H01L27/11582 , H01L29/7926
摘要： A nonvolatile memory device and a method of forming the same, the device including a semiconductor substrate; a plurality of gate patterns stacked on the semiconductor substrate; inter-gate dielectric patterns between the gate patterns; active pillars sequentially penetrating the gate patterns and the inter-gate dielectric patterns to contact the semiconductor substrate; and a gate insulating layer between the active pillars and the gate patterns, wherein corners of the gate patterns adjacent to the active pillars are rounded.
摘要翻译：非易失性存储器件及其形成方法，所述器件包括半导体衬底; 堆叠在所述半导体衬底上的多个栅极图案; 栅极图案之间的栅极间电介质图案; 依次穿过栅极图案和栅极间电介质图案以接触半导体衬底的有源支柱; 以及在活性柱和栅极图案之间的栅极绝缘层，其中与活性柱相邻的栅极图案的角部是圆形的。

7. 发明申请

US20120068255A1 THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICES 有权
标题翻译：三维半导体存储器件
公开(公告)号：US20120068255A1
公开(公告)日：2012-03-22
申请号：US13220376
申请日：2011-08-29
申请人： Changhyun LEE , Byoungkeun SON , Hyejin CHO
发明人： Changhyun LEE , Byoungkeun SON , Hyejin CHO
IPC分类号： H01L29/792
CPC分类号： H01L27/11582 , H01L27/11565 , H01L27/1157 , H01L29/7926
摘要： Three-dimensional (3D) nonvolatile memory devices include a substrate having a well region of second conductivity type (e.g., P-type) therein and a common source region of first conductivity type (e.g., N-type) on the well region. A recess is provided, which extends partially (or completely) through the common source region. A vertical stack of nonvolatile memory cells are provided on the substrate. This vertical stack of nonvolatile memory cells includes a vertical stack of spaced-apart gate electrodes and a vertical active region, which extends on sidewalls of the vertical stack of spaced-apart gate electrodes and on a sidewall of the recess. Gate dielectric layers are provided, which extend between respective ones of the vertical stack of spaced-apart gate electrodes and the vertical active region. The gate dielectric layers may include a composite of a tunnel insulating layer, a charge storage layer, a relatively high bandgap barrier dielectric layer and a blocking insulating layer having a relatively high dielectric strength.
摘要翻译：三维（3D）非易失性存储器件包括其中具有第二导电类型（例如，P型）的阱区和在该区域上具有第一导电类型（例如，N型）的公共源极区的衬底。设置有通过共同源极区域部分（或完全）延伸的凹部。在基板上提供了一堆非易失性存储单元。这种垂直堆叠的非易失性存储单元包括间隔开的栅电极的垂直叠层和垂直有源区，该垂直有源区延伸在间隔开的栅电极的垂直叠层的侧壁上并在凹槽的侧壁上延伸。提供栅介电层，其在相互间隔开的栅电极的垂直叠层和垂直有源区之间延伸。栅极电介质层可以包括隧道绝缘层，电荷存储层，相对高的带隙势垒介电层和具有相对高的介电强度的阻挡绝缘层的复合材料。

8. 发明申请

US20130114345A1 NONVOLATILE MEMORY DEVICE AND DRIVING METHOD THEREOF 有权
公开(公告)号：US20130114345A1
公开(公告)日：2013-05-09
申请号：US13654973
申请日：2012-10-18
申请人： Changhyun LEE
发明人： Changhyun LEE
IPC分类号： G11C16/12
CPC分类号： G11C16/10 , G11C16/0483 , G11C16/3459
摘要： According to example embodiments, a nonvolatile memory device includes a plurality of strings having a plurality of serially-connected selection transistors and a plurality of memory cells connected in series to one end of the serially-connected selection transistors. A control logic is configured to perform a program operation for setting a threshold voltage of at least one of the serially-connected selection transistors.

9. 发明申请

US20150340093A1 NONVOLATILE MEMORY DEVICE AND DRIVING METHOD THEREOF 审中-公开
标题翻译：非易失性存储器件及其驱动方法
公开(公告)号：US20150340093A1
公开(公告)日：2015-11-26
申请号：US14819428
申请日：2015-08-06
申请人： Changhyun LEE
发明人： Changhyun LEE
IPC分类号： G11C16/04 , G11C16/34 , G11C16/10
CPC分类号： G11C16/10 , G11C16/0483 , G11C16/3459
摘要： According to example embodiments, a nonvolatile memory device includes a plurality of strings having a plurality of serially-connected selection transistors and a plurality of memory cells connected in series to one end of the serially-connected selection transistors. A control logic is configured to perform a program operation for setting a threshold voltage of at least one of the serially-connected selection transistors.
摘要翻译：根据示例性实施例，非易失性存储器件包括具有多个串联连接的选择晶体管和与串联连接的选择晶体管的一端串联连接的多个存储单元的多个串。控制逻辑被配置为执行用于设置串联连接的选择晶体管中的至少一个的阈值电压的编程操作。

10. 发明申请

US20140029344A1 NONVOLATILE MEMORY DEVICE, PROGRAMMING METHOD THEREOF AND MEMORY SYSTEM INCLUDING THE SAME 审中-公开
标题翻译：非易失性存储器件，其编程方法和包括其的存储器系统
公开(公告)号：US20140029344A1
公开(公告)日：2014-01-30
申请号：US14043256
申请日：2013-10-01
申请人： Changhyun LEE , Jinman HAN , Doogon KIM , Sunghoi HUR , Jongin YUN
发明人： Changhyun LEE , Jinman HAN , Doogon KIM , Sunghoi HUR , Jongin YUN
IPC分类号： G11C16/10
CPC分类号： G11C16/107 , G11C16/0483 , G11C16/10 , G11C2213/71 , H01L27/11578 , H01L27/11582 , H01L29/7926
摘要： Provided is a programming method of a nonvolatile memory device. The nonvolatile memory device includes a substrate and a plurality of memory cells which are stacked in the direction perpendicular to the substrate. The programming method applies a first voltage to a selected bit line connected to at least two memory strings in same column including a memory cell of the plurality of memory cell to be programmed, applies a second voltage to an unselected bit line connected to at least two memory strings in same column including a memory cell of the plurality of memory cell to be program-prohibited, applies a third voltage to a selected string selection line connected to at least two memory strings in same row, applies a fourth voltage to an unselected string selection line connected to at least two memory strings in same row, and applies a program operation voltage to a plurality of word lines, each word line connected to each corresponding memory cell in the memory string, wherein the first to third voltages are positive voltages.
摘要翻译：提供了一种非易失性存储器件的编程方法。非易失性存储器件包括基板和沿垂直于基板的方向堆叠的多个存储单元。编程方法将第一电压施加到连接到包括要编程的多个存储器单元的存储单元的同一列中的至少两个存储器串的选定位线，将第二电压施加到连接至少两个的未选定位线包含要被编程禁止的多个存储单元的存储单元的同一列中的存储器串向同一行中连接到至少两个存储器串的所选择的串选择线施加第三电压，将第四电压施加到未选择的串选择线连接到同一行中的至少两个存储器串，并且将编程操作电压施加到多个字线，每个字线连接到存储器串中的每个对应的存储单元，其中第一至第三电压是正电压。

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