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1. 发明授权

US06171930B2 Device isolation structure and device isolation method for a semiconductor power integrated circuit 有权
标题翻译：半导体功率集成电路的器件隔离结构和器件隔离方法
公开(公告)号：US06171930B2
公开(公告)日：2001-01-09
申请号：US09233463
申请日：1999-01-20
申请人： Chang-Jae Lee , Jae-Il Ju
发明人： Chang-Jae Lee , Jae-Il Ju
IPC分类号： H01L2176
CPC分类号： H01L21/3081 , H01L21/76264 , H01L21/76281 , H01L21/76283
摘要： The present invention relates to a device isolation structure and a device solation method in a semiconductor power IC. The device isolation structure according to the present invention includes: a semiconductor substrate including a high voltage region and a low voltage region; a trench overlapping the high voltage device region of the semiconductor substrate and an interfacing region formed between the high voltage device region and the low voltage device region; a fourth insulating film, a fifth insulating film, and a conductive film sequentially layered in the trench; a first insulating film pattern formed on the semiconductor substrate including the trench; and field insulating films respectively formed on the trench and on a portion of an upper surface of the semiconductor substrate which is exposed out of the first insulating film pattern. The present invention has several advantages concerning manufacturing costs and reliability, some of which being achieved by forming a thermal oxide film in an empty space of the conductive film by which oxygen is permeated thereinto and thus restraining breakdown from being generated between high voltage devices at a high voltage.
摘要翻译：本发明涉及半导体功率IC中的器件隔离结构和器件固定方法。根据本发明的器件隔离结构包括：包括高电压区域和低电压区域的半导体衬底; 与半导体衬底的高压器件区域重叠的沟槽和形成在高电压器件区域和低电压器件区域之间的界面区域; 第四绝缘膜，第五绝缘膜和顺序层叠在沟槽中的导电膜; 形成在包括沟槽的半导体衬底上的第一绝缘膜图案; 以及分别形成在所述沟槽上和所述半导体衬底的从所述第一绝缘膜图案露出的所述上表面的一部分上的场绝缘膜。本发明具有制造成本和可靠性方面的几个优点，其中一些优点是通过在导电膜的空的空间中形成热氧化膜来实现的，氧空气通过氧化膜渗入其中，从而抑制在高压装置之间产生的击穿高压。

2. 发明授权

US06353254B1 Device isolation structure and device isolation method for a semiconductor power integrated circuit 有权
标题翻译：半导体功率集成电路的器件隔离结构和器件隔离方法
公开(公告)号：US06353254B1
公开(公告)日：2002-03-05
申请号：US09717304
申请日：2000-11-22
申请人： Chang-Jae Lee , Jae-Il Ju
发明人： Chang-Jae Lee , Jae-Il Ju
IPC分类号： H01L2900
CPC分类号： H01L21/3081 , H01L21/76264 , H01L21/76281 , H01L21/76283
摘要： The present invention relates to a device isolation structure and a device isolation method in a semiconductor power IC. The device isolation structure according to the present invention includes: a semiconductor substrate including a high voltage region and a low voltage region; a trench overlapping the high voltage device region of the semiconductor substrate and an interfacing region formed between the high voltage device region and the low voltage device region; a fourth insulating film, a fifth insulating film, and a conductive film sequentially layered in the trench; a first insulating film pattern formed on the semiconductor substrate including the trench; and field insulating films respectively formed on the trench and on a portion of an upper surface of the semiconductor substrate which is exposed out of the first insulating film pattern. The present invention has several advantages concerning manufacturing costs and reliability, some of which being achieved by forming a thermal oxide film in an empty space of the conductive film by which oxygen is permeated thereinto and thus restraining breakdown from being generated between high voltage devices at a high voltage.
摘要翻译：本发明涉及半导体功率IC中的器件隔离结构和器件隔离方法。根据本发明的器件隔离结构包括：包括高电压区域和低电压区域的半导体衬底; 与半导体衬底的高压器件区域重叠的沟槽和形成在高电压器件区域和低电压器件区域之间的界面区域; 第四绝缘膜，第五绝缘膜和顺序层叠在沟槽中的导电膜; 形成在包括沟槽的半导体衬底上的第一绝缘膜图案; 以及分别形成在所述沟槽上和所述半导体衬底的从所述第一绝缘膜图案露出的所述上表面的一部分上的场绝缘膜。本发明具有制造成本和可靠性方面的几个优点，其中一些优点是通过在导电膜的空的空间中形成热氧化膜来实现的，氧空气通过氧化膜渗入其中，从而抑制在高压装置之间产生的击穿高压。

3. 发明申请

US20060049462A1 High voltage transistor and method for fabricating the same 有权
标题翻译：高压晶体管及其制造方法
公开(公告)号：US20060049462A1
公开(公告)日：2006-03-09
申请号：US11223413
申请日：2005-09-08
申请人： Jae-Il Ju
发明人： Jae-Il Ju
IPC分类号： H01L23/62 , H01L29/76
CPC分类号： H01L29/7809 , H01L21/823885 , H01L29/66734 , H01L29/7813
摘要： A high voltage transistor operating through a high voltage and a method for fabricating the same are provided. The high voltage transistor includes: an insulation layer on a substrate; an N+-type drain junction region on the insulation layer; an N−-type drain junction region on the N+-type drain junction region; a P−-type body region provided in a trench region of the N−-type drain junction region; a plurality of gate patterns including a gate insulation layer and a gate conductive layer in other trench regions bordered by the P−-type body region and the N−-type drain junction region; a plurality of source regions contacted to a source electrode on the P−-type body region; and a plurality of N+-type drain regions contacted to the N−-type drain junction region and individual drain electrodes.
摘要翻译：提供了通过高电压工作的高压晶体管及其制造方法。高压晶体管包括：基板上的绝缘层; 绝缘层上的N + + +型漏极结区域; N + +型漏极结区域上的N + - 型漏极结区域; 设置在N + - 型漏极结区域的沟槽区域中的P + - SUP体型区域; 多个栅极图案，其包括在由P + - 型体区域和N - 型 - 类型的漏极结区域界定的其它沟槽区域中的栅极绝缘层和栅极导电层地区; 多个源区域，与源极体区域上的源电极接触; 以及与N +型漏极结区域和各个漏电极接触的多个N + +型漏极区域。

4. 发明授权

US07247532B2 High voltage transistor and method for fabricating the same 有权
标题翻译：高压晶体管及其制造方法
公开(公告)号：US07247532B2
公开(公告)日：2007-07-24
申请号：US11223413
申请日：2005-09-08
申请人： Jae-Il Ju
发明人： Jae-Il Ju
IPC分类号： H01L21/8238
CPC分类号： H01L29/7809 , H01L21/823885 , H01L29/66734 , H01L29/7813
摘要： A high voltage transistor operating through a high voltage and a method for fabricating the same are provided. The high voltage transistor includes: an insulation layer on a substrate; an N+-type drain junction region on the insulation layer; an N−-type drain junction region on the N+-type drain junction region; a P−-type body region provided in a trench region of the N−-type drain junction region; a plurality of gate patterns including a gate insulation layer and a gate conductive layer in other trench regions bordered by the P−-type body region and the N−-type drain junction region; a plurality of source regions contacted to a source electrode on the P−-type body region; and a plurality of N+-type drain regions contacted to the N−-type drain junction region and individual drain electrodes.
摘要翻译：提供了通过高电压工作的高压晶体管及其制造方法。高压晶体管包括：基板上的绝缘层; 绝缘层上的N + + +型漏极结区域; N + +型漏极结区域上的N + - 型漏极结区域; 设置在N + - 型漏极结区域的沟槽区域中的P + - SUP体型区域; 多个栅极图案，其包括在由P + - 型体区域和N - 型 - 类型的漏极结区域界定的其它沟槽区域中的栅极绝缘层和栅极导电层地区; 多个源区域，与源极体区域上的源电极接触; 以及与N +型漏极结区域和各个漏电极接触的多个N + +型漏极区域。

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