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1. 发明授权

US08660276B2 Driving circuit for a sound outputting apparatus 失效
标题翻译：声音输出装置的驱动电路
公开(公告)号：US08660276B2
公开(公告)日：2014-02-25
申请号：US13309397
申请日：2011-12-01
申请人： Chang-Chih Lin , Hung-Dar Wang , Pei-Cheng Huang
发明人： Chang-Chih Lin , Hung-Dar Wang , Pei-Cheng Huang
IPC分类号： H04R3/00
CPC分类号： H04R3/00
摘要： A driving circuit for a sound outputting apparatus includes a H-bridge and a charge pump established by six switches for driving two types of loudspeakers, respectively. The six switches include two common switches to be configured in the H-bridge and the charge pump, thereby reducing the costs and circuit area of the driving circuit.
摘要翻译：用于声音输出装置的驱动电路包括分别由用于驱动两种扬声器的六个开关建立的H桥和电荷泵。六个开关包括在H桥和电荷泵中配置的两个公共开关，从而降低驱动电路的成本和电路面积。

2. 发明申请

US20050013019A1 Method of maintaining photolithographic precision alignment after wafer bonding process 失效
标题翻译：在晶片接合工艺之后保持光刻精密对准的方法
公开(公告)号：US20050013019A1
公开(公告)日：2005-01-20
申请号：US10722603
申请日：2003-11-28
申请人： Chung-Yang Tseng , Shih-Chin Gong , Reuy-Shing Huang , Tong-An Lee , Kuo-Chung Chan , Hung-Dar Wang
发明人： Chung-Yang Tseng , Shih-Chin Gong , Reuy-Shing Huang , Tong-An Lee , Kuo-Chung Chan , Hung-Dar Wang
IPC分类号： G02B7/02 , H01L21/18 , H01L21/76
CPC分类号： B81C3/002 , H01L21/187 , H01L23/544 , H01L2223/54426 , H01L2223/54453 , H01L2224/83894 , H01L2924/01322 , Y10S438/928 , Y10S438/975 , Y10S438/977
摘要： A method of maintaining photolithographic precision alignment for a wafer after being bonded, wherein two cavities are formed at the rear surface of a top wafer at the position corresponding to alignment marks made on a bottom wafer. The depth of both cavities is deeper than that of a final membrane structure. The top wafer is then bonded to the bottom wafer which already has alignment marks and a microstructure. This bonded wafer is annealed to intensify its bonding strength. After that, a thinning process is applied until the thickness of the top wafer is reduced to thinner than the cavity depth such that the alignment marks are emerged in the top wafer cavities thereby serving as alignment marks for any exposure equipment.
摘要翻译：在粘合后保持晶片的光刻精密对准的方法，其中在对应于在底部晶片上制成的对准标记的位置处在顶部晶片的后表面处形成两个空腔。两个腔的深度都比最终膜结构深。然后将顶部晶片结合到已经具有对准标记和微结构的底部晶片。退火该接合晶片以增强其结合强度。之后，施加变薄处理直到顶部晶片的厚度减小到比腔深度更薄，使得对准标记出现在顶部晶片空腔中，从而用作任何曝光设备的对准标记。

3. 发明授权

US06967145B2 Method of maintaining photolithographic precision alignment after wafer bonding process 失效
公开(公告)号：US06967145B2
公开(公告)日：2005-11-22
申请号：US10722603
申请日：2003-11-28
申请人： Chung-Yang Tseng , Shih-Chin Gong , Reuy-shing Huang , Tong-An Lee , Kuo-Chung Chan , Hung-Dar Wang
发明人： Chung-Yang Tseng , Shih-Chin Gong , Reuy-shing Huang , Tong-An Lee , Kuo-Chung Chan , Hung-Dar Wang
IPC分类号： G02B7/02 , H01L21/18 , H01L21/76
CPC分类号： B81C3/002 , H01L21/187 , H01L23/544 , H01L2223/54426 , H01L2223/54453 , H01L2224/83894 , H01L2924/01322 , Y10S438/928 , Y10S438/975 , Y10S438/977
摘要： A method of maintaining photolithographic precision alignment for a wafer after being bonded, wherein two cavities are formed at the rear surface of a top wafer at the position corresponding to alignment marks made on a bottom wafer. The depth of both cavities is deeper than that of a final membrane structure. The top wafer is then bonded to the bottom wafer which already has alignment marks and a microstructure. This bonded wafer is annealed to intensify its bonding strength. After that, a thinning process is applied until the thickness of the top wafer is reduced to thinner than the cavity depth such that the alignment marks are emerged in the top wafer cavities thereby serving as alignment marks for any exposure equipment.

4. 发明授权

US06864176B2 Fabrication process for bonded wafer precision layer thickness control and its non-destructive measurement method 有权
标题翻译：贴片晶圆精密层厚度控制及其非破坏性测量方法的制作工艺
公开(公告)号：US06864176B2
公开(公告)日：2005-03-08
申请号：US10155008
申请日：2002-05-28
申请人： Hung-Dar Wang , Ruey-Shing Huang , Shih-Chin Gong , Chung-Yang Tseng
发明人： Hung-Dar Wang , Ruey-Shing Huang , Shih-Chin Gong , Chung-Yang Tseng
IPC分类号： G01B11/06 , B24B37/04 , B24B49/03 , B24B49/12 , C23F1/02 , H01L21/304 , H01L23/544 , H01L21/302
CPC分类号： B24B37/005 , H01L22/34
摘要： A measurement method for the thinned thickness of the silicon wafer, wherein thickness inspection patterns are fabricated onto the silicon wafer substrate by anisotropic etching, and then the wafer is polished with a polisher; thus a wafer with desired thickness can be obtained after the polish is proceeded; the thickness of the upper wafer is determined by the said inspection patterns, then the wafer is sorted by thickness; thus it can be applied to the MEMS micromachined devices that in need of the wafer with such precise thickness.
摘要翻译：一种用于通过各向异性蚀刻在硅晶片衬底上制造厚度检查图案的硅晶片厚度测量方法，然后用抛光机抛光晶片; 因此可以在抛光进行后获得具有所需厚度的晶片; 上晶片的厚度由所述检查图案确定，然后按厚度分选晶片; 因此可以将其应用于需要具有这种精确厚度的晶片的MEMS微加工器件。

5. 发明授权

US06838303B2 Silicon pressure sensor and the manufacturing method thereof 有权
标题翻译：硅压力传感器及其制造方法
公开(公告)号：US06838303B2
公开(公告)日：2005-01-04
申请号：US10390628
申请日：2003-03-19
申请人： Hung-Dar Wang , Shih-Chin Gong
发明人： Hung-Dar Wang , Shih-Chin Gong
IPC分类号： G01L9/00 , H01L21/00
CPC分类号： G01L9/0054
摘要： The present invention relates to a silicon pressure sensor that in need of three strips of piezoresistors on each side and the manufacturing method thereof; wherein, the impurity concentration of the piezoresistors are about 1019-1020 cm−3 in order to reduce the influence of temperature; the lead between the piezoresistors (namely the internal connection lead) is a highly-doping interconnect (about 1021 cm−3) fabricated along the direction with minimum piezoresistance coefficient; with regard to the connection circuit for connecting the piezoresistors with the external Wheatstone bridge circuit (namely the external connection circuit), of which one end near the inner side of the membrane is also fabricated along the direction with minimum piezoresistance coefficient, and another end of the lead near the edge of the membrane is a interconnect that is perpendicular to the diaphragm, and is connected out to the external circuit; with this structure, the four resistors of the Whetstone bridge are balanced and symmetrized, thus the zero offset caused by the variations in resistance of the bridge can be reduced in order to simplify the signal-processing circuit.

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