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1. 发明授权

US10170495B2 Stacked memory device, optical proximity correction (OPC) verifying method, method of designing layout of stacked memory device, and method of manufacturing stacked memory device 有权
公开(公告)号：US10170495B2
公开(公告)日：2019-01-01
申请号：US15402258
申请日：2017-01-10
申请人： Chang-Bum Kim , Sung-Hoon Kim , Woo-Joung Kim , Hyang-Ja Yang
发明人： Chang-Bum Kim , Sung-Hoon Kim , Woo-Joung Kim , Hyang-Ja Yang
IPC分类号： G06F17/50 , H01L27/11582 , G03F1/36 , H01L21/027 , H01L27/11568 , H01L27/11573 , H01L27/11575
摘要： An optical proximity correction (OPC) verifying method including checking a first location of a first pattern in a layout of a stacked memory device, calculating a shift value of the first pattern according to the first location, obtaining a difference value between the first location and a second location of a second pattern formed through an OPC with respect to the first pattern, and determining whether the OPC is to be performed again, based on the shift value and the difference value.

2. 发明申请

US20070020858A1 Layout structure of MOS transistors and methods of disposing MOS transistors on an active region 失效
标题翻译： MOS晶体管的布局结构和在有源区上设置MOS晶体管的方法
公开(公告)号：US20070020858A1
公开(公告)日：2007-01-25
申请号：US11485341
申请日：2006-07-13
申请人： Hyang-Ja Yang , Su-Jin Park , Uk-Rae Cho , Sung-Hoon Kim
发明人： Hyang-Ja Yang , Su-Jin Park , Uk-Rae Cho , Sung-Hoon Kim
IPC分类号： H01L21/8234
CPC分类号： H01L27/0203 , H01L21/823418 , H01L21/823481
摘要： In a layout structure of a plurality of metal oxide semiconductor (MOS) transistors, the layout structure may include a first group of MOS transistors having first drain regions and first source regions that are individually allocated to a group active region that is isolated from all sides by a trench isolation, and a second group of MOS transistors having second drain regions and second source regions allocated to the group active region. The second group is disposed between the first group and an edge of the group active region. One or both of the first drain regions and first source regions are not in contact with an edge of the trench isolation in a length direction of a finger-type gate electrode.
摘要翻译：在多个金属氧化物半导体（MOS）晶体管的布局结构中，布局结构可以包括具有第一漏极区域的第一组MOS晶体管和分别分配给与所有侧面隔离的组有源区域的第一源极区域通过沟槽隔离，以及第二组MOS晶体管，其具有分配给组有源区的第二漏极区和第二源极区。第二组布置在第一组与组有源区的边缘之间。第一漏极区域和第一源极区域中的一个或两个不与指状栅电极的长度方向上的沟槽隔离边缘接触。

3. 发明授权

US07525173B2 Layout structure of MOS transistors on an active region 失效
标题翻译：有源区MOS晶体管的布局结构
公开(公告)号：US07525173B2
公开(公告)日：2009-04-28
申请号：US11485341
申请日：2006-07-13
申请人： Hyang-Ja Yang , Su-Jin Park , Uk-Rae Cho , Sung-Hoon Kim
发明人： Hyang-Ja Yang , Su-Jin Park , Uk-Rae Cho , Sung-Hoon Kim
IPC分类号： H01L29/78
CPC分类号： H01L27/0203 , H01L21/823418 , H01L21/823481
摘要： In a layout structure of a plurality of metal oxide semiconductor (MOS) transistors, the layout structure may include a first group of MOS transistors having first drain regions and first source regions that are individually allocated to a group active region that is isolated from all sides by a trench isolation, and a second group of MOS transistors having second drain regions and second source regions allocated to the group active region. The second group is disposed between the first group and an edge of the group active region. One or both of the first drain regions and first source regions are not in contact with an edge of the trench isolation in a length direction of a finger-type gate electrode.
摘要翻译：在多个金属氧化物半导体（MOS）晶体管的布局结构中，布局结构可以包括具有第一漏极区域的第一组MOS晶体管和分别分配给与所有侧面隔离的组有源区域的第一源极区域通过沟槽隔离，以及第二组MOS晶体管，其具有分配给组有源区的第二漏极区和第二源极区。第二组布置在第一组与组有源区的边缘之间。第一漏极区域和第一源极区域中的一个或两个不与指状栅电极的长度方向上的沟槽隔离边缘接触。

4. 发明授权

US08279703B2 Sub-word line driver circuit and semiconductor memory device having the same 有权
标题翻译：子字线驱动电路和半导体存储器件
公开(公告)号：US08279703B2
公开(公告)日：2012-10-02
申请号：US12839454
申请日：2010-07-20
申请人： Hyang-Ja Yang , Jeong-Soo Park
发明人： Hyang-Ja Yang , Jeong-Soo Park
IPC分类号： G11C8/00 , H01L29/76 , H01L21/70
CPC分类号： G11C8/08
摘要： A sub-word line driver includes a substrate, a plurality of gate lines and at least one gate tab. The substrate includes a plurality of isolation areas and a plurality of active areas, where the two active areas are separated by each isolation area, and the isolation areas and the active areas are extended in a first direction and are arranged in a second direction perpendicular to the first direction. The plurality of gate lines are formed on the substrate, where the gate lines are extended in a second direction and are arranged in the first direction. The at least one gate tab is formed on the substrate, where the at least one gate tab is extended in the first direction to cover the isolation area. Incorrect operation of the sub-word line driver may be prevented, and a power consumption of the sub-word line driver may be reduced.
摘要翻译：子字线驱动器包括衬底，多个栅极线和至少一个栅极突起。衬底包括多个隔离区域和多个有效区域，其中两个有源区域由每个隔离区域分开，并且隔离区域和有源区域在第一方向上延伸并且沿垂直于第一个方向。多个栅极线形成在基板上，其中栅极线沿第二方向延伸并且沿第一方向布置。所述至少一个栅极突片形成在所述基板上，其中所述至少一个栅极突片在所述第一方向上延伸以覆盖所述隔离区域。可以防止子字线驱动器的不正确的操作，并且可以减少子字线驱动器的功耗。

5. 发明授权

US07808852B2 Semiconductor memory device and layout method thereof 有权
标题翻译：半导体存储器件及其布局方法
公开(公告)号：US07808852B2
公开(公告)日：2010-10-05
申请号：US12230570
申请日：2008-09-02
申请人： Hyang-Ja Yang , Wol-Jin Lee
发明人： Hyang-Ja Yang , Wol-Jin Lee
IPC分类号： G11C7/00
CPC分类号： G11C7/12 , G11C7/18
摘要： Example embodiments relate to a semiconductor memory device, for example, a semiconductor memory device including an efficient layout circuit and method thereof. The method may include sharing a first active area between a first precharger and a second precharger and sharing a second active area between a third precharger and a fourth precharger. The semiconductor memory device may include a level shifter configured to receive a first precharge control signal and boost a logic high level of the first precharge control signal to an external power supply voltage level to output a boosted first precharge control signal. The semiconductor memory device may further include first, second, third and fourth prechargers. The first and third prechargers may be configured to precharge data signals transmitted to a first and second pair of local input/output data lines to the first precharge voltage in response to the boosted first precharge control signal during a data read operation.
摘要翻译：示例性实施例涉及半导体存储器件，例如包括有效布局电路的半导体存储器件及其方法。该方法可以包括在第一预充电器和第二预充电器之间共享第一有效区域并且在第三预充电器和第四预充电器之间共享第二有效区域。半导体存储器件可以包括电平移位器，其被配置为接收第一预充电控制信号并将第一预充电控制信号的逻辑高电平升高到外部电源电压电平以输出升压的第一预充电控制信号。半导体存储器件还可以包括第一，第二，第三和第四预充电器。第一和第三预充电器可以被配置为在数据读取操作期间响应于升压的第一预充电控制信号而将传输到第一和第二对本地输入/输出数据线的数据信号预充电到第一预充电电压。

6. 发明授权

US07405956B2 Line layout structure of semiconductor memory devices 有权
标题翻译：半导体存储器件的线路布局结构
公开(公告)号：US07405956B2
公开(公告)日：2008-07-29
申请号：US11227563
申请日：2005-09-15
申请人： Hyang-Ja Yang , Yun-Jin Jo
发明人： Hyang-Ja Yang , Yun-Jin Jo
IPC分类号： G11C5/06
CPC分类号： G11C5/063 , H01L27/1104
摘要： A line layout structure of semiconductor memory device comprises first metal wire lines forming a bit line coupled to a memory cell, second metal wire lines disposed substantially orthogonal to the first metal wire lines and over the first metal wire lines, the second metal wire lines forming a section word line electrically coupled to the memory cell, and third metal wire lines disposed substantially parallel to the second metal wire lines and over the second metal wire lines, the third metal wire lines forming a first power line or signal line.
摘要翻译：半导体存储器件的线路布局结构包括形成耦合到存储单元的位线的第一金属线线，与第一金属线线基本上正交并且与第一金属线线基本上正交的第二金属线线，第二金属线线形成电耦合到所述存储单元的部分字线以及基本上平行于所述第二金属线线设置并且在所述第二金属线路上的第三金属线线，所述第三金属线线形成第一电力线或信号线。

7. 发明授权

US07057963B2 Dual port SRAM memory 有权
标题翻译：双端口SRAM存储器
公开(公告)号：US07057963B2
公开(公告)日：2006-06-06
申请号：US10926441
申请日：2004-08-25
申请人： Hyang-Ja Yang
发明人： Hyang-Ja Yang
IPC分类号： G11C8/00
CPC分类号： G11C8/16
摘要： The layout structure of a dual port SRAM (Static Random Access Memory) includes a read bit line adjacently positioned to a complementary read bit line, and a write bit line positioned adjacent to a complementary write bit line, to provide a shield between the read and write lines for preventing cross-talk caused during read and write operations.
摘要翻译：双端口SRAM（静态随机存取存储器）的布局结构包括相邻于互补读位线的读位线和位于互补写位线附近的写位线，以提供读和写位线之间的屏蔽写入线，用于防止在读写操作期间引起的串扰。

8. 发明申请

US20050047256A1 Dual port SRAM memory 有权
标题翻译：双端口SRAM存储器
公开(公告)号：US20050047256A1
公开(公告)日：2005-03-03
申请号：US10926441
申请日：2004-08-25
申请人： Hyang-Ja Yang
发明人： Hyang-Ja Yang
IPC分类号： H01L27/11 , G11C8/16 , G11C11/00 , G11C8/00
CPC分类号： G11C8/16
摘要： The layout structure of a dual port SRAM (Static Random Access Memory) includes a read bit line adjacently positioned to a complementary read bit line, and a write bit line positioned adjacent to a complementary write bit line, to provide a shield between the read and write lines for preventing cross-talk caused during read and write operations.
摘要翻译：双端口SRAM（静态随机存取存储器）的布局结构包括相邻于互补读位线的读位线和位于互补写位线附近的写位线，以提供读和写位线之间的屏蔽写入线，用于防止在读写操作期间引起的串扰。

9. 发明授权

US06359313B1 Electrostatic discharge protection transistor for a semiconductor chip 有权
标题翻译：用于半导体芯片的静电放电保护晶体管
公开(公告)号：US06359313B1
公开(公告)日：2002-03-19
申请号：US09313882
申请日：1999-05-18
申请人： Hyang-Ja Yang , Kook-Hwan Kwon
发明人： Hyang-Ja Yang , Kook-Hwan Kwon
IPC分类号： H01L2362
CPC分类号： H01L27/0266 , H01L23/60 , H01L2924/0002 , H01L2924/00
摘要： An electrostatic discharge (ESD) protection transistor for discharging current from an ESD event present on an input/output pad. The ESD protection transistor is capable of improved discharging of excessive current without damage to the semiconductor device and to the ESD protection transistor itself. The ESD protection transistor includes a first conductive line connecting an input/output pad to the source and drain of the transistor at multiple points preventing the convergence of an excessive current at a certain point and ESD damage to the transistor. The transistor also includes a second conductive line formed on an insulating layer such that it does not overlap with the first conductive line.
摘要翻译：用于从存在于输入/输出焊盘上的ESD事件放电的静电放电（ESD）保护晶体管。 ESD保护晶体管能够改善对过电流的放电，而不损坏半导体器件和ESD保护晶体管本身。 ESD保护晶体管包括在多个点处将输入/输出焊盘连接到晶体管的源极和漏极的第一导线，以防止某一点处的过大电流的会聚和对晶体管的ESD损坏。晶体管还包括形成在绝缘层上的第二导线，使得其不与第一导线重叠。

10. 发明授权

US07999297B2 Semiconductor device having stacked decoupling capacitors 有权
标题翻译：具有层叠去耦电容器的半导体器件
公开(公告)号：US07999297B2
公开(公告)日：2011-08-16
申请号：US11370365
申请日：2006-03-08
申请人： Hyang-Ja Yang
发明人： Hyang-Ja Yang
IPC分类号： H01L27/108
CPC分类号： H01L27/1108 , H01L23/642 , H01L27/0688 , H01L27/105 , H01L27/10808 , H01L27/10897 , H01L27/11 , H01L27/1104 , H01L27/1116 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device having transistors formed on different layers of a stack structure includes a stacked capacitor cluster, wherein a stacked capacitor of the stacked capacitor cluster includes an insulation layer of a transistor of the semiconductor device, and at least a first conduction layer and a second conduction layer disposed above and below the insulation layer, wherein the stacked capacitor is a decoupling capacitor of the stacked capacitor cluster connected in parallel between a first line and a second line.
摘要翻译：具有形成在堆叠结构的不同层上的晶体管的半导体器件包括层叠电容器簇，其中层叠电容器簇的堆叠电容器包括半导体器件的晶体管的绝缘层，以及至少第一导电层和第二导电层导电层，其设置在所述绝缘层的上方和下方，其中所述堆叠电容器是在第一线路和第二线路之间并联连接的所述堆叠电容器集群的去耦电容器。

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