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1. 发明申请

US20120307542A1 LOCAL BIT LINES AND METHODS OF SELECTING THE SAME TO ACCESS MEMORY ELEMENTS IN CROSS-POINT ARRAYS 有权
标题翻译：本地位线及其选择方法可以在交叉点阵列中访问记忆元素
公开(公告)号：US20120307542A1
公开(公告)日：2012-12-06
申请号：US13588461
申请日：2012-08-17
申请人： Chang Hua Siau , Christophe Chevallier , Darrell Rinerson , Seow Fong Lim , Sri Namala
发明人： Chang Hua Siau , Christophe Chevallier , Darrell Rinerson , Seow Fong Lim , Sri Namala
IPC分类号： G11C5/02
CPC分类号： G11C5/025 , G11C5/02 , G11C8/00 , G11C11/00 , G11C13/0002 , G11C13/0007 , G11C13/0023 , G11C13/0026 , G11C13/0028 , G11C13/004 , G11C13/0061 , G11C13/0069 , G11C13/0097 , G11C2213/77 , H01L21/82 , H01L27/2481 , H01L45/16
摘要： Embodiments relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to implement a memory architecture that includes local bit lines for accessing subsets of memory elements, such as memory elements based on third dimensional memory technology. In at least some embodiments, an integrated circuit includes a cross-point memory array formed above a logic layer. The cross-point memory array includes X-lines and Y-lines, of which at least one Y-line includes groups of Y-line portions. Each of the Y-line portions can be arranged in parallel with other Y-line portions within a group of the Y-line portions. Also included are memory elements disposed between a subset of the X-lines and the group of the Y-line portions. In some embodiments, a decoder is configured to select a Y-line portion from the group of Y-line portions to access a subset of the memory elements.
摘要翻译：实施例通常涉及半导体和存储器技术，更具体地，涉及用于实现存储器架构的系统，集成电路和方法，该存储器架构包括用于访问诸如基于第三维存储器技术的存储器元件的存储器元件的子集的本地位线。在至少一些实施例中，集成电路包括形成在逻辑层上方的交叉点存储器阵列。交叉点存储器阵列包括X线和Y线，其中至少一条Y线包括Y线部分的组。每个Y线部分可以与一组Y线部分内的其它Y线部分平行地布置。还包括设置在X线的子集和Y线部分的组之间的存储器元件。在一些实施例中，解码器被配置为从Y组部分组中选择Y线部分以访问存储器元件的子集。

2. 发明申请

US20080144357A1 Method for sensing a signal in a two-terminal memory array having leakage current 有权
标题翻译：用于感测具有漏电流的双端存储器阵列中的信号的方法
公开(公告)号：US20080144357A1
公开(公告)日：2008-06-19
申请号：US12072813
申请日：2008-02-28
申请人： Chang Hua Siau , Christophe Chevallier , Darrell Rinerson
发明人： Chang Hua Siau , Christophe Chevallier , Darrell Rinerson
IPC分类号： G11C11/00 , G11C7/02
CPC分类号： G11C11/16 , G11C11/5685 , G11C13/0007 , G11C13/004 , G11C2013/0054 , G11C2013/0057 , G11C2211/5634 , G11C2213/31 , G11C2213/32 , G11C2213/34 , G11C2213/77
摘要： A two-terminal memory array includes a plurality of first and second conductive traces. An address unit operatively applies a select voltage across a selected pair of the first and second conductive traces and applies a non-select voltage potential to unselected traces. A total current flowing in the selected first conductive trace and a leakage current flowing through unselected second conductive traces are sensed by a sense unit in a one cycle or a two cycle pre-read operation. The total and leakage currents can be combined with a reference signal to derive a data signal indicative of one of a plurality of conductivity profiles that represent stored data. The conductivity profiles can be stored in a resistive state memory element that is electrically in series with the selected first and second conductive traces.
摘要翻译：双端存储器阵列包括多个第一和第二导电迹线。地址单元可操作地对所选择的第一和第二导电迹线对施加选择电压，并将非选择电压电势施加到未选择的迹线。在所选择的第一导电迹线中流动的总电流和流过未选择的第二导电迹线的漏电流在一个周期或两个周期的预读操作中由感测单元感测。总和漏电流可以与参考信号组合以导出指示表示存储的数据的多个电导率分布之一的数据信号。电导率分布可以存储在与所选择的第一和第二导电迹线电串联的电阻状态存储元件中。

3. 发明授权

US07379364B2 Sensing a signal in a two-terminal memory array having leakage current 有权
标题翻译：感测具有漏电流的双端存储器阵列中的信号
公开(公告)号：US07379364B2
公开(公告)日：2008-05-27
申请号：US11583446
申请日：2006-10-19
申请人： Chang Hua Siau , Christophe Chevallier , Darrell Rinerson
发明人： Chang Hua Siau , Christophe Chevallier , Darrell Rinerson
IPC分类号： G11C7/02
CPC分类号： G11C11/16 , G11C11/5685 , G11C13/0007 , G11C13/004 , G11C2013/0054 , G11C2013/0057 , G11C2211/5634 , G11C2213/31 , G11C2213/32 , G11C2213/34 , G11C2213/77
摘要： A two-terminal memory array includes a plurality of first and second conductive traces. An address unit operatively applies a select voltage across a selected pair of the first and second conductive traces and applies a non-select voltage potential to unselected traces. A total current flowing in the selected first conductive trace and a leakage current flowing through unselected second conductive traces are sensed by a sense unit in a one cycle or a two cycle pre-read operation. The total and leakage currents can be combined with a reference signal to derive a data signal indicative of one of a plurality of conductivity profiles that represent stored data. The conductivity profiles can be stored in a resistive state memory element that is electrically in series with the selected first and second conductive traces.
摘要翻译：双端存储器阵列包括多个第一和第二导电迹线。地址单元可操作地对所选择的第一和第二导电迹线对施加选择电压，并将非选择电压电势施加到未选择的迹线。在所选择的第一导电迹线中流动的总电流和流过未选择的第二导电迹线的漏电流在一个周期或两个周期的预读操作中由感测单元感测。总和漏电流可以与参考信号组合以导出指示表示存储的数据的多个电导率分布之一的数据信号。电导率分布可以存储在与所选择的第一和第二导电迹线电串联的电阻状态存储元件中。

4. 发明申请

US20080094876A1 SENSING A SIGNAL IN A TWO-TERMINAL MEMORY ARRAY HAVING LEAKAGE CURRENT 有权
标题翻译：在具有漏电流的两个终端存储器阵列中感测信号
公开(公告)号：US20080094876A1
公开(公告)日：2008-04-24
申请号：US11583446
申请日：2006-10-19
申请人： Chang Hua Siau , Christophe Chevallier , Darrell Rinerson
发明人： Chang Hua Siau , Christophe Chevallier , Darrell Rinerson
IPC分类号： G11C11/00 , G11C7/02
CPC分类号： G11C11/16 , G11C11/5685 , G11C13/0007 , G11C13/004 , G11C2013/0054 , G11C2013/0057 , G11C2211/5634 , G11C2213/31 , G11C2213/32 , G11C2213/34 , G11C2213/77
摘要： A two-terminal memory array includes a plurality of first and second conductive traces. An address unit operatively applies a select voltage across a selected pair of the first and second conductive traces and applies a non-select voltage potential to unselected traces. A total current flowing in the selected first conductive trace and a leakage current flowing through unselected second conductive traces are sensed by a sense unit in a one cycle or a two cycle pre-read operation. The total and leakage currents can be combined with a reference signal to derive a data signal indicative of one of a plurality of conductivity profiles that represent stored data. The conductivity profiles can be stored in a resistive state memory element that is electrically in series with the selected first and second conductive traces.
摘要翻译：双端存储器阵列包括多个第一和第二导电迹线。地址单元可操作地对所选择的第一和第二导电迹线对施加选择电压，并将非选择电压电势施加到未选择的迹线。在所选择的第一导电迹线中流动的总电流和流过未选择的第二导电迹线的漏电流在一个周期或两个周期的预读取操作中由感测单元感测。总和漏电流可以与参考信号组合以导出指示表示存储的数据的多个电导率分布之一的数据信号。电导率分布可以存储在与所选择的第一和第二导电迹线电串联的电阻状态存储元件中。

5. 发明授权

US08897050B2 Local bit lines and methods of selecting the same to access memory elements in cross-point arrays 有权
标题翻译：本地位线及其选择方法可以访问交叉点阵列中的存储器元件
公开(公告)号：US08897050B2
公开(公告)日：2014-11-25
申请号：US13588461
申请日：2012-08-17
申请人： Chang Hua Siau , Christophe Chevallier , Darrell Rinerson , Seow Fong Lim , Sri Namala
发明人： Chang Hua Siau , Christophe Chevallier , Darrell Rinerson , Seow Fong Lim , Sri Namala
IPC分类号： G11C5/02 , H01L21/82 , G11C8/00 , G11C11/00
CPC分类号： G11C5/025 , G11C5/02 , G11C8/00 , G11C11/00 , G11C13/0002 , G11C13/0007 , G11C13/0023 , G11C13/0026 , G11C13/0028 , G11C13/004 , G11C13/0061 , G11C13/0069 , G11C13/0097 , G11C2213/77 , H01L21/82 , H01L27/2481 , H01L45/16
摘要： Embodiments relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to implement a memory architecture that includes local bit lines for accessing subsets of memory elements, such as memory elements based on third dimensional memory technology. In at least some embodiments, an integrated circuit includes a cross-point memory array formed above a logic layer. The cross-point memory array includes X-lines and Y-lines, of which at least one Y-line includes groups of Y-line portions. Each of the Y-line portions can be arranged in parallel with other Y-line portions within a group of the Y-line portions. Also included are memory elements disposed between a subset of the X-lines and the group of the Y-line portions. In some embodiments, a decoder is configured to select a Y-line portion from the group of Y-line portions to access a subset of the memory elements.
摘要翻译：实施例通常涉及半导体和存储器技术，更具体地，涉及用于实现存储器架构的系统，集成电路和方法，该存储器架构包括用于访问诸如基于第三维存储器技术的存储器元件的存储器元件的子集的本地位线。在至少一些实施例中，集成电路包括形成在逻辑层上方的交叉点存储器阵列。交叉点存储器阵列包括X线和Y线，其中至少一条Y线包括Y线部分的组。每个Y线部分可以与一组Y线部分内的其它Y线部分平行地布置。还包括设置在X线的子集和Y线部分的组之间的存储器元件。在一些实施例中，解码器被配置为从Y组部分组中选择Y线部分以访问存储器元件的子集。

6. 发明授权

US08737151B2 Low read current architecture for memory 有权
标题翻译：低读取存储体系结构
公开(公告)号：US08737151B2
公开(公告)日：2014-05-27
申请号：US13252934
申请日：2011-10-04
申请人： Bruce Bateman , Darrell Rinerson , Christophe Chevallier , Chang Hua Siau
发明人： Bruce Bateman , Darrell Rinerson , Christophe Chevallier , Chang Hua Siau
IPC分类号： G11C7/00
CPC分类号： G11C13/004 , G11C7/12 , G11C7/22 , G11C13/0002 , G11C13/0004 , G11C13/0007 , G11C13/0009 , G11C13/0011 , G11C13/0026 , G11C13/0028 , G11C13/0061 , G11C13/0069 , G11C2013/0045 , G11C2013/0054 , G11C2213/11 , G11C2213/31 , G11C2213/32 , G11C2213/53 , G11C2213/71 , G11C2213/77
摘要： A low read current architecture for memory. Bit lines of a cross point memory array are allowed to be charged by a selected word line until a minimum voltage differential between a memory state and a reference level is assured.
摘要翻译：用于存储器的低读取当前体系结构。允许交叉点存储器阵列的位线被选择的字线充电，直到确保存储器状态和参考电平之间的最小电压差。

7. 发明授权

US07372753B1 Two-cycle sensing in a two-terminal memory array having leakage current 有权
标题翻译：具有漏电流的双端存储器阵列中的双周期感测
公开(公告)号：US07372753B1
公开(公告)日：2008-05-13
申请号：US11583676
申请日：2006-10-19
申请人： Darrell Rinerson , Christophe Chevallier , Chang Hua Siau
发明人： Darrell Rinerson , Christophe Chevallier , Chang Hua Siau
IPC分类号： G11C7/02
CPC分类号： G11C11/16 , G11C13/004 , G11C2013/0057
摘要： A two-terminal memory array includes a plurality of first and second conductive traces. An address unit operatively applies a select voltage across a selected pair of the first and second conductive traces and applies a non-select voltage potential to unselected traces. A total current flowing in the selected first conductive trace and a leakage current flowing through unselected second conductive traces are sensed by a sense unit in a one cycle or a two cycle pre-read operation. The total and leakage currents can be combined with a reference signal to derive a data signal indicative of one of a plurality of conductivity profiles that represent stored data. The conductivity profiles can be stored in a resistive state memory element that is electrically in series with the selected first and second conductive traces.
摘要翻译：双端存储器阵列包括多个第一和第二导电迹线。地址单元可操作地对所选择的第一和第二导电迹线对施加选择电压，并将非选择电压电势施加到未选择的迹线。在所选择的第一导电迹线中流动的总电流和流过未选择的第二导电迹线的漏电流在一个周期或两个周期的预读操作中由感测单元感测。总和漏电流可以与参考信号组合以导出指示表示存储的数据的多个电导率分布之一的数据信号。电导率分布可以存储在与所选择的第一和第二导电迹线电串联的电阻状态存储元件中。

8. 发明申请

US20080094929A1 TWO-CYCLE SENSING IN A TWO-TERMINAL MEMORY ARRAY HAVING LEAKAGE CURRENT 有权
标题翻译：具有漏电流的两端存储器阵列中的双周期感测
公开(公告)号：US20080094929A1
公开(公告)日：2008-04-24
申请号：US11583676
申请日：2006-10-19
申请人： Darrell Rinerson , Christophe Chevallier , Chang Hua Siau
发明人： Darrell Rinerson , Christophe Chevallier , Chang Hua Siau
IPC分类号： G11C11/00 , G11C7/02
CPC分类号： G11C11/16 , G11C13/004 , G11C2013/0057
摘要： A two-terminal memory array includes a plurality of first and second conductive traces. An address unit operatively applies a select voltage across a selected pair of the first and second conductive traces and applies a non-select voltage potential to unselected traces. A total current flowing in the selected first conductive trace and a leakage current flowing through unselected second conductive traces are sensed by a sense unit in a one cycle or a two cycle pre-read operation. The total and leakage currents can be combined with a reference signal to derive a data signal indicative of one of a plurality of conductivity profiles that represent stored data. The conductivity profiles can be stored in a resistive state memory element that is electrically in series with the selected first and second conductive traces.
摘要翻译：双端存储器阵列包括多个第一和第二导电迹线。地址单元可操作地对所选择的第一和第二导电迹线对施加选择电压，并将非选择电压电势施加到未选择的迹线。在所选择的第一导电迹线中流动的总电流和流过未选择的第二导电迹线的漏电流在一个周期或两个周期的预读操作中由感测单元感测。总和漏电流可以与参考信号组合以导出指示表示存储的数据的多个电导率分布之一的数据信号。电导率分布可以存储在与所选择的第一和第二导电迹线电串联的电阻状态存储元件中。

9. 发明授权

US08270193B2 Local bit lines and methods of selecting the same to access memory elements in cross-point arrays 有权
标题翻译：本地位线及其选择方法可以访问交叉点阵列中的存储器元件
公开(公告)号：US08270193B2
公开(公告)日：2012-09-18
申请号：US12657911
申请日：2010-01-29
申请人： Chang Hua Siau , Christophe Chevallier , Darrell Rinerson , Seow Fong Lim , Sri Rama Namala
发明人： Chang Hua Siau , Christophe Chevallier , Darrell Rinerson , Seow Fong Lim , Sri Rama Namala
IPC分类号： G11C5/02
CPC分类号： G11C5/025 , G11C5/02 , G11C8/00 , G11C11/00 , G11C13/0002 , G11C13/0007 , G11C13/0023 , G11C13/0026 , G11C13/0028 , G11C13/004 , G11C13/0061 , G11C13/0069 , G11C13/0097 , G11C2213/77 , H01L21/82 , H01L27/2481 , H01L45/16
摘要： Embodiments relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to implement a memory architecture that includes local bit lines for accessing subsets of memory elements, such as memory elements based on third dimensional memory technology. In at least some embodiments, an integrated circuit includes a cross-point memory array formed above a logic layer. The cross-point memory array includes X-lines and Y-lines, of which at least one Y-line includes groups of Y-line portions. Each of the Y-line portions can be arranged in parallel with other Y-line portions within a group of the Y-line portions. Also included are memory elements disposed between a subset of the X-lines and the group of the Y-line portions. In some embodiments, a decoder is configured to select a Y-line portion from the group of Y-line portions to access a subset of the memory elements.
摘要翻译：实施例通常涉及半导体和存储器技术，更具体地，涉及用于实现存储器架构的系统，集成电路和方法，该存储器架构包括用于访问诸如基于第三维存储器技术的存储器元件的存储器元件的子集的本地位线。在至少一些实施例中，集成电路包括形成在逻辑层上方的交叉点存储器阵列。交叉点存储器阵列包括X线和Y线，其中至少一条Y线包括Y线部分的组。每个Y线部分可以与一组Y线部分内的其它Y线部分平行地布置。还包括设置在X线的子集和Y线部分的组之间的存储器元件。在一些实施例中，解码器被配置为从Y组部分组中选择Y线部分以访问存储器元件的子集。

10. 发明授权

US08031545B2 Low read current architecture for memory 有权
标题翻译：低读取存储体系结构
公开(公告)号：US08031545B2
公开(公告)日：2011-10-04
申请号：US12799168
申请日：2010-04-19
申请人： Darrell Rinerson , Christophe Chevallier , Chang Hua Siau
发明人： Darrell Rinerson , Christophe Chevallier , Chang Hua Siau
IPC分类号： G11C7/00
CPC分类号： G11C7/12 , G11C7/22 , G11C13/0007 , G11C13/0026 , G11C13/004 , G11C13/0061 , G11C13/02 , G11C2013/0054 , G11C2213/11 , G11C2213/31 , G11C2213/32 , G11C2213/71 , G11C2213/77
摘要： A low read current architecture for memory. Bit lines of a cross point memory array are allowed to be charged by a selected word line until a minimum voltage differential between a memory state and a reference level is assured.
摘要翻译：用于存储器的低读取当前体系结构。允许交叉点存储器阵列的位线被选择的字线充电，直到确保存储器状态和参考电平之间的最小电压差。

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