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1. 发明授权

US08816732B2 Capactive load PLL with calibration loop 有权
标题翻译：带校准回路的负载负载PLL
公开(公告)号：US08816732B2
公开(公告)日：2014-08-26
申请号：US13530136
申请日：2012-06-22
申请人： Chan-Hong Chern , Tao Wen Chung , Ming-Chieh Huang , Chih-Chang Lin , Tsung-Ching Huang , Fu-Lung Hsueh
发明人： Chan-Hong Chern , Tao Wen Chung , Ming-Chieh Huang , Chih-Chang Lin , Tsung-Ching Huang , Fu-Lung Hsueh
IPC分类号： H03L7/06
CPC分类号： H03L7/103 , H03L7/097 , H03L7/0995 , H03L7/1072 , H03L7/18 , H03L2207/06
摘要： A circuit includes a capacitive-load voltage controlled oscillator having an input configured to receive a first input signal and an output configured to output an oscillating output signal. A calibration circuit is coupled to the voltage controlled oscillator and is configured to output one or more control signals to the capacitive-load voltage controlled oscillator for adjusting a frequency of the oscillating output signal. The calibration circuit is configured to output the one or more control signals in response to a comparison of an input voltage to at least one reference voltage.
摘要翻译：电路包括电容负载压控振荡器，其具有被配置为接收第一输入信号的输入和被配置为输出振荡输出信号的输出。校准电路耦合到压控振荡器，并被配置为将一个或多个控制信号输出到电容负载压控振荡器，用于调整振荡输出信号的频率。校准电路被配置为响应于输入电压与至少一个参考电压的比较而输出一个或多个控制信号。

2. 发明申请

US20140038085A1 Automatic Misalignment Balancing Scheme for Multi-Patterning Technology 有权
标题翻译：多图案化技术的自动对准平衡方案
公开(公告)号：US20140038085A1
公开(公告)日：2014-02-06
申请号：US13562436
申请日：2012-07-31
申请人： Chan-Hong Chern , Tao Wen Chung , Ming-Chieh Huang , Chih-Chang Lin , Tsung-Ching (Jim) Huang , Fu-Lung Hsueh
发明人： Chan-Hong Chern , Tao Wen Chung , Ming-Chieh Huang , Chih-Chang Lin , Tsung-Ching (Jim) Huang , Fu-Lung Hsueh
IPC分类号： G06F17/50 , G03F1/68
CPC分类号： G03F7/70466 , G03F7/70433 , G06F17/5077
摘要： Some aspects of the present disclosure provide for a method of automatically balancing mask misalignment for multiple patterning layers to minimize the consequences of mask misalignment. In some embodiments, the method defines a routing grid for one or more double patterning layers within an IC layout. The routing grid has a plurality of vertical grid lines extending along a first direction and a plurality of horizontal grid lines extending along a second, orthogonal direction. Alternating lines of the routing grid in a given direction (e.g., the horizontal and vertical direction) are assigned different colors. Shapes on the double patterning layers are then routed along the routing grid in a manner that alternates between different colored grid lines. By routing in such a manner, variations in capacitive coupling caused by mask misalignment are reduced.
摘要翻译：本公开的一些方面提供了一种自动平衡多个图案化层的掩模未对准的方法，以最小化掩模未对准的后果。在一些实施例中，该方法定义了IC布局内的一个或多个双图案化层的布线网格。路由网格具有沿着第一方向延伸的多个垂直网格线和沿着第二正交方向延伸的多个水平网格线。在给定方向（例如，水平和垂直方向）上布线网格的交替线被分配不同的颜色。然后双重图案化层上的形状沿着布线网格以不同颜色的网格线之间交替的方式布线。通过以这种方式进行布线，减少了由掩模未对准引起的电容耦合的变化。

3. 发明申请

US20140028407A1 Reconfigurable and Auto-Reconfigurable Resonant Clock 有权
标题翻译：可重构和自动重新配置的谐振时钟
公开(公告)号：US20140028407A1
公开(公告)日：2014-01-30
申请号：US13558670
申请日：2012-07-26
申请人： Chan-Hong Chern , Tao Wen Chung , Chih-Chang Lin , Ming-Chieh Huang , Tsung-Ching Huang , Fu-Lung Hsueh
发明人： Chan-Hong Chern , Tao Wen Chung , Chih-Chang Lin , Ming-Chieh Huang , Tsung-Ching Huang , Fu-Lung Hsueh
IPC分类号： H03B5/12
CPC分类号： G06F1/10 , H03B5/12 , H03B5/32 , H03K5/15
摘要： The present disclosure relates to a resonant clock system having a driver component, a clock load capacitor, and a reconfigurable inductor array. The driver component generates a driven input signal. The clock load capacitor is configured to receive the driven input signal. The inductor array is configured to have an effective inductance according to a selected frequency. The inductor array also generates a resonant signal at the selected frequency using the effective inductance.
摘要翻译：本公开涉及具有驱动器部件，时钟负载电容器和可重构电感器阵列的谐振时钟系统。驱动器组件产生驱动输入信号。时钟负载电容器被配置为接收驱动输入信号。电感器阵列被配置为具有根据选定频率的有效电感。电感器阵列还使用有效电感在选定频率处产生谐振信号。

4. 发明授权

US08588358B2 Clock and data recovery using LC voltage controlled oscillator and delay locked loop 有权
标题翻译：使用LC压控振荡器和延迟锁定环的时钟和数据恢复
公开(公告)号：US08588358B2
公开(公告)日：2013-11-19
申请号：US13045788
申请日：2011-03-11
申请人： Chan-Hong Chern , Chih-Chang Lin , Ming-Chieh Huang , Fu-Lung Hsueh
发明人： Chan-Hong Chern , Chih-Chang Lin , Ming-Chieh Huang , Fu-Lung Hsueh
IPC分类号： H04L7/00
CPC分类号： H04L7/033 , H03L7/0807 , H03L7/081 , H03L7/113 , H04L7/0337
摘要： A clock and data recovery (CDR) circuit includes an inductor-capacitor voltage controlled oscillator (LCVCO) configured to generate a clock signal with a clock frequency. A delay locked loop (DLL) is configured to receive the clock signal from the LCVCO and generate multiple clock phases. A charge pump is configured to control the LCVCO. A phase detector is configured to receive a data input and the multiple clock phases from the DLL, and to control the first charge pump in order to align a data edge of the data input and the multiple clock phases.
摘要翻译：时钟和数据恢复（CDR）电路包括被配置为产生具有时钟频率的时钟信号的电感器 - 电容器压控振荡器（LCVCO）。延迟锁定环（DLL）被配置为从LCVCO接收时钟信号并生成多个时钟相位。电荷泵配置为控制LCVCO。相位检测器被配置为从DLL接收数据输入和多个时钟相位，并且控制第一电荷泵以便对准数据输入和多个时钟相位的数据沿。

5. 发明授权

US08493124B2 Low minimum power supply voltage level shifter 有权
标题翻译：低最小电源电压电平转换器
公开(公告)号：US08493124B2
公开(公告)日：2013-07-23
申请号：US12843479
申请日：2010-07-26
申请人： Chan-Hong Chern , Fu-Lung Hsueh , Ming-Chieh Huang , Chih-Chang Lin
发明人： Chan-Hong Chern , Fu-Lung Hsueh , Ming-Chieh Huang , Chih-Chang Lin
IPC分类号： H03L5/00
CPC分类号： H03K19/018521
摘要： A level shifter includes one PMOS and two NMOS transistors. A source of the first NMOS transistor is coupled to a low power supply voltage. An input signal is coupled to a gate of the first NMOS transistor and a source of the second NMOS transistor. The input signal has a voltage level up to a first power supply voltage. A source of the PMOS transistor is coupled to a second power supply voltage, higher than the first power supply voltage. An output signal is coupled between the PMOS and the first NMOS transistors. The first NMOS transistor is arranged to pull down the output signal when the input signal is a logical 1, and the second NMOS transistor is arranged to enable the PMOS transistor to pull up the output signal to a logical 1 at the second power supply voltage when the input signal is a logical 0.
摘要翻译：电平移位器包括一个PMOS和两个NMOS晶体管。第一NMOS晶体管的源极耦合到低电源电压。输入信号耦合到第一NMOS晶体管的栅极和第二NMOS晶体管的源极。输入信号具有高达第一电源电压的电压电平。 PMOS晶体管的源极耦合到高于第一电源电压的第二电源电压。输出信号耦合在PMOS和第一NMOS晶体管之间。第一NMOS晶体管被布置为当输入信号为逻辑1时下拉输出信号，并且第二NMOS晶体管被布置为使得PMOS晶体管能够以第二电源电压将输出信号上拉至逻辑1，输入信号为逻辑0。

6. 发明授权

US08436671B2 Level shifters having diode-connected devices for input-output interfaces 有权
标题翻译：电平移位器具有用于输入 - 输出接口的二极管连接器件
公开(公告)号：US08436671B2
公开(公告)日：2013-05-07
申请号：US12859456
申请日：2010-08-19
申请人： Chan-Hong Chern , Fu-Lung Hsueh , Chih-Chang Lin , Yuwen Swei , Ming-Chieh Huang
发明人： Chan-Hong Chern , Fu-Lung Hsueh , Chih-Chang Lin , Yuwen Swei , Ming-Chieh Huang
IPC分类号： H03L5/00
CPC分类号： H03K3/02 , H03K19/018521 , H03K19/018528
摘要： A level shifter includes an input node, an output node, a pull-up transistor, a pull-down transistor, and at least one diode-connected device coupled between the pull-up transistor and the pull-down transistor. The level shifter is arranged to be coupled to a high power supply voltage, to receive an input signal having a first voltage level at the input node, and to supply an output signal having a second voltage level at the output node. The high power supply voltage is higher than the first voltage level. The at least one diode-connected device allows the output signal to be pulled up to about a first diode voltage drop below the high power supply voltage and/or to be pulled down to about a second diode voltage drop above ground. The first diode voltage drop and the second diode voltage drop are from the at least one diode-connected device.
摘要翻译：电平移位器包括输入节点，输出节点，上拉晶体管，下拉晶体管以及耦合在上拉晶体管和下拉晶体管之间的至少一个二极管连接器件。电平移位器被布置为耦合到高电源电压，以在输入节点处接收具有第一电压电平的输入信号，并且在输出节点处提供具有第二电压电平的输出信号。高电源电压高于第一电压电平。所述至少一个二极管连接的装置允许输出信号被上拉到大约低于高电源电压的第一二极管电压降和/或被下拉到大约地面上的第二二极管电压降。第一二极管电压降和第二二极管压降来自至少一个二极管连接的器件。

7. 发明授权

US08847652B2 Reconfigurable and auto-reconfigurable resonant clock 有权
标题翻译：可重构和自动重构谐振时钟
公开(公告)号：US08847652B2
公开(公告)日：2014-09-30
申请号：US13558670
申请日：2012-07-26
申请人： Chan-Hong Chern , Tao Wen Chung , Chih-Chang Lin , Ming-Chieh Huang , Tsung-Ching Huang , Fu-Lung Hsueh
发明人： Chan-Hong Chern , Tao Wen Chung , Chih-Chang Lin , Ming-Chieh Huang , Tsung-Ching Huang , Fu-Lung Hsueh
IPC分类号： G06F1/10 , H03K5/15
CPC分类号： G06F1/10 , H03B5/12 , H03B5/32 , H03K5/15
摘要： The present disclosure relates to a resonant clock system having a driver component, a clock load capacitor, and a reconfigurable inductor array. The driver component generates a driven input signal. The clock load capacitor is configured to receive the driven input signal. The inductor array is configured to have an effective inductance according to a selected frequency. The inductor array also generates a resonant signal at the selected frequency using the effective inductance.
摘要翻译：本公开涉及具有驱动器部件，时钟负载电容器和可重构电感器阵列的谐振时钟系统。驱动器组件产生驱动输入信号。时钟负载电容器被配置为接收驱动输入信号。电感器阵列被配置为具有根据选定频率的有效电感。电感器阵列还使用有效电感在选定频率处产生谐振信号。

8. 发明授权

US08709684B2 Automatic misalignment balancing scheme for multi-patterning technology 有权
标题翻译：多图案化技术的自动对准平衡方案
公开(公告)号：US08709684B2
公开(公告)日：2014-04-29
申请号：US13562436
申请日：2012-07-31
申请人： Chan-Hong Chern , Tao Wen Chung , Ming-Chieh Huang , Chih-Chang Lin , Tsung-Ching (Jim) Huang , Fu-Lung Hsueh
发明人： Chan-Hong Chern , Tao Wen Chung , Ming-Chieh Huang , Chih-Chang Lin , Tsung-Ching (Jim) Huang , Fu-Lung Hsueh
IPC分类号： G03F1/68
CPC分类号： G03F7/70466 , G03F7/70433 , G06F17/5077
摘要： Some aspects of the present disclosure provide for a method of automatically balancing mask misalignment for multiple patterning layers to minimize the consequences of mask misalignment. In some embodiments, the method defines a routing grid for one or more double patterning layers within an IC layout. The routing grid has a plurality of vertical grid lines extending along a first direction and a plurality of horizontal grid lines extending along a second, orthogonal direction. Alternating lines of the routing grid in a given direction (e.g., the horizontal and vertical direction) are assigned different colors. Shapes on the double patterning layers are then routed along the routing grid in a manner that alternates between different colored grid lines. By routing in such a manner, variations in capacitive coupling caused by mask misalignment are reduced.
摘要翻译：本公开的一些方面提供了一种自动平衡多个图案化层的掩模未对准的方法，以最小化掩模未对准的后果。在一些实施例中，该方法定义了IC布局内的一个或多个双图案化层的布线网格。路由网格具有沿着第一方向延伸的多个垂直网格线和沿着第二正交方向延伸的多个水平网格线。在给定方向（例如，水平和垂直方向）上布线网格的交替线被分配不同的颜色。然后双重图案化层上的形状沿着布线网格以不同颜色的网格线之间交替的方式布线。通过以这种方式进行布线，减少了由掩模未对准引起的电容耦合的变化。

9. 发明授权

US08570068B2 Circuit for reducing negative bias temperature instability 有权
标题翻译：降低负偏压温度不稳定性的电路
公开(公告)号：US08570068B2
公开(公告)日：2013-10-29
申请号：US12768899
申请日：2010-04-28
申请人： Chan-Hong Chern , Fu-Lung Hsueh , Ming-Chieh Huang , Bryan Sheffield , Chih-Chang Lin
发明人： Chan-Hong Chern , Fu-Lung Hsueh , Ming-Chieh Huang , Bryan Sheffield , Chih-Chang Lin
IPC分类号： H03K19/0175
CPC分类号： H03K19/01855 , H03K3/012 , H03K3/356008 , H03K3/35625 , H03K19/0016 , H03K19/0963
摘要： A circuit includes an operational PMOS transistor of a logic gate driver. A control circuit is configured to turn off the operational PMOS transistor during a standby mode. The circuit also includes a sacrificial PMOS transistor coupled to an output node. The operational PMOS transistor is coupled to the output node. The sacrificial PMOS transistor is configured to keep the output node at a logical 1 during the standby mode.
摘要翻译：电路包括逻辑门驱动器的操作PMOS晶体管。控制电路被配置为在待机模式期间关闭操作PMOS晶体管。电路还包括耦合到输出节点的牺牲PMOS晶体管。操作PMOS晶体管耦合到输出节点。牺牲PMOS晶体管被配置为在待机模式期间将输出节点保持在逻辑1。

10. 发明授权

US08698566B2 Phase locked loop calibration 有权
标题翻译：锁相环校准
公开(公告)号：US08698566B2
公开(公告)日：2014-04-15
申请号：US13252498
申请日：2011-10-04
申请人： Chan-Hong Chern , Ming-Chieh Huang , Tao Wen Chung , Chih-Chang Lin , Fu-Lung Hsueh , Yuwen Swei
发明人： Chan-Hong Chern , Ming-Chieh Huang , Tao Wen Chung , Chih-Chang Lin , Fu-Lung Hsueh , Yuwen Swei
IPC分类号： H03L7/085 , H03L7/10 , H03B5/12
CPC分类号： H03L7/102 , H03L7/099 , H03L2207/06
摘要： An inductor-capacitor phase locked loop (LCPLL) includes an inductor-capacitor voltage controlled oscillator (LCVCO) that provides an output frequency. A calibration circuit includes two comparators and provides a coarse tune signal to the LCVCO. The two comparators respectively compare the loop filter signal with a first reference voltage and a second reference voltage that is higher than the first reference voltage to supply a first and second comparator output, respectively. The calibration circuit is capable of adjusting the coarse tune signal continuously in voltage values and adjusts the coarse tune signal based on the two comparator outputs. A loop filter provides a loop filter signal to the calibration circuit and a fine tune signal to the LCVCO. A coarse tune frequency range is greater than a fine tune frequency range.
摘要翻译：电感 - 电容器锁相环（LCPLL）包括提供输出频率的电感 - 电容压控振荡器（LCVCO）。校准电路包括两个比较器，并向LCVCO提供粗调信号。两个比较器分别将环路滤波器信号与第一参考电压和高于第一参考电压的第二参考电压进行比较，以分别提供第一和第二比较器输出。校准电路能够在电压值中连续调整粗调信号，并根据两个比较器输出调整粗调信号。环路滤波器向校准电路提供环路滤波器信号，并向LCVCO提供微调信号。粗调频率范围大于微调频率范围。

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