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1. 发明申请

US20130127433A1 METHOD OF OPERATING VOLTAGE REGULATOR 有权
标题翻译：操作电压调节器的方法
公开(公告)号：US20130127433A1
公开(公告)日：2013-05-23
申请号：US13744037
申请日：2013-01-17
申请人： Chan-Hong CHERN , Tzu Ching CHANG , Min-Shueh YUAN , Yuwen SWEI , Chih-Chang LIN , Chiang PU , Ming-Chieh HUANG , Kuoyuan HSU
发明人： Chan-Hong CHERN , Tzu Ching CHANG , Min-Shueh YUAN , Yuwen SWEI , Chih-Chang LIN , Chiang PU , Ming-Chieh HUANG , Kuoyuan HSU
IPC分类号： G05F1/44
CPC分类号： H02M3/158 , G05F1/44 , G05F1/56
摘要： A method of operating a voltage regulator circuit includes generating a control signal by an amplifier of the voltage regulator circuit. The control signal is generated based on a reference signal at an inverting input of the amplifier and a feedback signal at a non-inverting input of the amplifier. A driving current flowing toward an output node of the voltage regulator circuit is generated by a driver responsive to the control signal, and the driver is coupled between a first power node and the output node. The feedback signal is generated responsive to a voltage level at the output node. A transistor, coupled between the output node and a second power node, is caused to operate in saturation mode during a period while the voltage regulator circuit is operating.
摘要翻译：一种操作电压调节器电路的方法包括由稳压器电路的放大器产生控制信号。控制信号基于放大器的反相输入处的参考信号和放大器的非反相输入端的反馈信号而产生。通过响应于控制信号的驱动器产生朝向电压调节器电路的输出节点流动的驱动电流，并且驱动器耦合在第一功率节点和输出节点之间。响应于输出节点处的电压电平产生反馈信号。耦合在输出节点和第二功率节点之间的晶体管在电压调节器电路工作期间的一段时间内使其工作在饱和模式。

2. 发明申请

US20140266114A1 METHOD OF OPERATING VOLTAGE REGULATOR 有权
标题翻译：操作电压调节器的方法
公开(公告)号：US20140266114A1
公开(公告)日：2014-09-18
申请号：US14291426
申请日：2014-05-30
申请人： Chan-Hong CHERN , Tzu Ching CHANG , Min-Shueh YUAN , Yuwen SWEI , Chih-Chang LIN , Chiang PU , Ming-Chieh HUANG , Kuoyuan HSU
发明人： Chan-Hong CHERN , Tzu Ching CHANG , Min-Shueh YUAN , Yuwen SWEI , Chih-Chang LIN , Chiang PU , Ming-Chieh HUANG , Kuoyuan HSU
IPC分类号： H02M3/158
CPC分类号： H02M3/158 , G05F1/44 , G05F1/56
摘要： A voltage regulator circuit comprises an amplifier having an inverting input and a non-inverting input. The amplifier is configured to generate a control signal based on a reference signal at the inverting input of the amplifier and a feedback signal at the non-inverting input of the amplifier. The voltage regulator circuit also comprises an output node, a first power node, a second power node, and a driver that generates a driving current flowing toward the output node in response to the control signal. The driver is coupled between the first power node and the output node. A first transistor having a gate is coupled between the output node and the second power node. A bias circuit outside the amplifier supplies a bias signal to the gate of the first transistor, which is configured to operate in a saturation mode based on the bias signal supplied by the bias circuit.
摘要翻译：电压调节器电路包括具有反相输入和非反相输入的放大器。放大器被配置为基于放大器的反相输入端处的参考信号和放大器的非反相输入端的反馈信号产生控制信号。电压调节器电路还包括响应于控制信号产生朝向输出节点流动的驱动电流的输出节点，第一功率节点，第二功率节点和驱动器。驱动器耦合在第一功率节点和输出节点之间。具有栅极的第一晶体管耦合在输出节点和第二功率节点之间。放大器外部的偏置电路向第一晶体管的栅极提供偏置信号，该偏置信号被配置为基于偏置电路提供的偏置信号在饱和模式下工作。

3. 发明申请

US20100253303A1 VOLTAGE REGULATOR WITH HIGH ACCURACY AND HIGH POWER SUPPLY REJECTION RATIO 有权
标题翻译：具有高精度和高功率抑制比的电压调节器
公开(公告)号：US20100253303A1
公开(公告)日：2010-10-07
申请号：US12750260
申请日：2010-03-30
申请人： Chan-Hong CHERN , Tzu Ching CHANG , Min-Shueh YUAN , Yuwen SWEI , Chih-Chang LIN , Chiang PU , Ming-Chieh HUANG , Kuoyuan HSU
发明人： Chan-Hong CHERN , Tzu Ching CHANG , Min-Shueh YUAN , Yuwen SWEI , Chih-Chang LIN , Chiang PU , Ming-Chieh HUANG , Kuoyuan HSU
IPC分类号： G05F1/10
CPC分类号： H02M3/158 , G05F1/44 , G05F1/56
摘要： A voltage regulator circuit with high accuracy and Power Supply Rejection Ratio (PSRR) is provided. In one embodiment, an op-amp with a voltage reference input to an inverting input has the first output connected to a PMOS transistor's gate. The PMOS transistor's source and drain are each connected to the power supply and the voltage regulator output. The voltage regulator output is connected to an NMOS transistor biased in saturation mode and a series of two resistors. The non-inverting input of the op-amp is connected in between the two resistors for the first feedback loop. The op-amp's second output is connected to the gate of the NMOS transistor through an AC-coupling capacitor for the second feedback loop. The op-amp's first output can be connected to the power supply voltage through a capacitor to further improve high frequency PSRR. In another embodiment, the role of PMOS and NMOS transistors is reversed.
摘要翻译：提供了具有高精度和电源抑制比（PSRR）的稳压电路。在一个实施例中，具有到反相输入的电压参考输入的运算放大器具有连接到PMOS晶体管的栅极的第一输出。 PMOS晶体管的源极和漏极各自连接到电源和稳压器输出。电压调节器输出连接到偏置在饱和模式的NMOS晶体管和一系列两个电阻。运算放大器的非反相输入端连接在第一个反馈回路的两个电阻之间。运算放大器的第二个输出通过用于第二反馈回路的交流耦合电容器连接到NMOS晶体管的栅极。运算放大器的第一个输出可以通过电容连接到电源电压，以进一步提高高频PSRR。在另一个实施例中，PMOS和NMOS晶体管的作用相反。

4. 发明申请

US20130099767A1 DRIVERS HAVING T-COIL STRUCTURES 有权
标题翻译：具有T型线圈结构的驱动器
公开(公告)号：US20130099767A1
公开(公告)日：2013-04-25
申请号：US13278742
申请日：2011-10-21
申请人： Ming-Chieh HUANG , Tao Wen CHUNG , Chan-Hong CHERN , Chih-Chang LIN , Yuwen SWEI , Chiang PU
发明人： Ming-Chieh HUANG , Tao Wen CHUNG , Chan-Hong CHERN , Chih-Chang LIN , Yuwen SWEI , Chiang PU
IPC分类号： G05F3/02
CPC分类号： H03H11/44 , H01S5/0427 , H04B10/504
摘要： A driver includes a first driver stage having at least one input node and at least one first output node. The first driver stage includes a T-coil structure that is disposed adjacent to the at least one first output node. The T-coil structure includes a first set of inductors each being operable to provide a first inductance. A second set of inductors are electrically coupled with the first set of inductors in a parallel fashion. The second set of inductors each are operable to provide a second inductance. A second driver stage is electrically coupled with the first driver stage.
摘要翻译：驱动器包括具有至少一个输入节点和至少一个第一输出节点的第一驱动器级。第一驱动级包括邻近于至少一个第一输出节点设置的T型线圈结构。 T型线圈结构包括第一组电感器，每个电感器可操作以提供第一电感。第二组电感器以并行方式与第一组电感器电耦合。第二组电感器可操作以提供第二电感。第二驱动级与第一驱动器级电耦合。

5. 发明申请

US20130120051A1 CIRCUIT AND METHOD FOR GENERATING CLOCK SIGNAL 有权
标题翻译：用于产生时钟信号的电路和方法
公开(公告)号：US20130120051A1
公开(公告)日：2013-05-16
申请号：US13737624
申请日：2013-01-09
申请人： Chiang PU , Ming-Chieh HUANG , Chan-Hong CHERN
发明人： Chiang PU , Ming-Chieh HUANG , Chan-Hong CHERN
IPC分类号： G05F1/10
CPC分类号： G05F1/10 , G11C7/22 , G11C7/222 , G11C11/406 , G11C11/40615 , G11C11/40626 , G11C2211/4065
摘要： A circuit includes a comparator, a first circuit, and a second circuit. The comparator includes a first input node, a second input node, and an output node. The first circuit is configured to generate a temperature-dependent reference current at the second input node of the comparator. The second circuit is coupled with the second input node of the comparator. The second circuit is configured to increase a voltage level at the second input node of the comparator in response to the temperature-dependent reference current when a signal at the output node of the comparator indicates a first comparison result, and decrease the voltage level at the second input node of the comparator when the signal at the output node of the comparator indicates a second comparison result.
摘要翻译：电路包括比较器，第一电路和第二电路。比较器包括第一输入节点，第二输入节点和输出节点。第一电路被配置为在比较器的第二输入节点处产生与温度相关的参考电流。第二电路与比较器的第二输入节点耦合。第二电路被配置为当比较器的输出节点处的信号指示第一比较结果时，响应于温度相关的参考电流来增加比较器的第二输入节点处的电压电平，并且降低电压电平当比较器的输出节点处的信号指示第二比较结果时，比较器的第二输入节点。

6. 发明申请

US20120026820A1 INTEGRATED CIRCUITS FOR PROVIDING CLOCK PERIODS AND OPERATING METHODS THEREOF 有权
标题翻译：用于提供时钟周期的集成电路及其操作方法
公开(公告)号：US20120026820A1
公开(公告)日：2012-02-02
申请号：US12844204
申请日：2010-07-27
申请人： Chiang PU , Ming-Chieh HUANG , Chan-Hong CHERN
发明人： Chiang PU , Ming-Chieh HUANG , Chan-Hong CHERN
IPC分类号： G11C7/00 , G05F1/10
CPC分类号： G05F1/10 , G11C7/22 , G11C7/222 , G11C11/406 , G11C11/40615 , G11C11/40626 , G11C2211/4065
摘要： An integrated circuit includes a capacitor. A switch is electrically coupled with the capacitor in a parallel fashion. A comparator includes a first input node, a second input node, and an output node. The second input node is electrically coupled with a first plate of the capacitor. The output node is electrically coupled with the switch. A transistor is electrically coupled with a second plate of the capacitor. A circuit is electrically coupled with a gate of the transistor. The circuit is configured to provide a bias voltage to the gate of the transistor so as to control a current that is supplied to charge the capacitor.
摘要翻译：集成电路包括电容器。开关以并联方式与电容器电耦合。比较器包括第一输入节点，第二输入节点和输出节点。第二输入节点与电容器的第一板电耦合。输出节点与开关电耦合。晶体管与电容器的第二板电耦合。电路与晶体管的栅极电耦合。电路被配置为向晶体管的栅极提供偏置电压，以便控制供给电容器充电的电流。

7. 发明申请

US20110267139A1 AUTOMATIC LEVEL CONTROL 有权
公开(公告)号：US20110267139A1
公开(公告)日：2011-11-03
申请号：US13177958
申请日：2011-07-07
申请人： Chiang PU , Ming-Chieh HUANG , Chan-Hong CHERN , Tien-Chun YANG
发明人： Chiang PU , Ming-Chieh HUANG , Chan-Hong CHERN , Tien-Chun YANG
IPC分类号： G05F1/10 , H03F3/45
CPC分类号： G01C19/5776
摘要： Some embodiments regard a circuit comprising: a high voltage transistor providing a resistance; an amplifier configured to receive a current and to convert the current to a first voltage that is used in a loop creating the current; and an automatic level control circuit that, based on an AC amplitude of the first voltage, adjusts a second voltage at a gate of the high voltage transistor and thereby adjusts the resistance and the first voltage; wherein the automatic level control circuit is configured to adjust the first voltage toward the first reference voltage if the first voltage differs from a first reference voltage.

8. 发明申请

US20100259311A1 LEVEL SHIFTERS, INTEGRATED CIRCUITS, SYSTEMS, AND METHODS FOR OPERATING THE LEVEL SHIFTERS 有权
标题翻译：水平变换器，集成电路，系统和操作水平移位器的方法
公开(公告)号：US20100259311A1
公开(公告)日：2010-10-14
申请号：US12717705
申请日：2010-03-04
申请人： Tien Chun YANG , Yuwen SWEI , Chih-Chang LIN , Chiang PU
发明人： Tien Chun YANG , Yuwen SWEI , Chih-Chang LIN , Chiang PU
IPC分类号： H03L5/00
CPC分类号： H03K19/017509 , H03K19/018521 , H05K13/00 , Y10T29/49117
摘要： A level shifter includes an input end being capable of receiving an input voltage signal. The input voltage signal includes a first state transition from a first voltage state to a second voltage state. An output end can output an output voltage signal having a second state transition from a third voltage state to the second voltage state corresponding to the first state transition of the input voltage signal. A driver stage is coupled between the input end and the output end. The driver stage includes a first transistor and a second transistor. Substantially immediately from a time corresponding to about a mean of voltage levels of the first voltage state and the second voltage state, the second voltage state is substantially free from being applied to a gate of the first transistor so as to substantially turn off the first transistor.
摘要翻译：电平移位器包括能够接收输入电压信号的输入端。输入电压信号包括从第一电压状态到第二电压状态的第一状态转变。输出端可以输出具有从第三电压状态到对应于输入电压信号的第一状态转换的第二电压状态的第二状态转换的输出电压信号。驱动级连接在输入端和输出端之间。驱动器级包括第一晶体管和第二晶体管。基本上从与第一电压状态和第二电压状态的电压电平的平均值相对应的时间基本上立即，第二电压状态基本上没有被施加到第一晶体管的栅极，以便基本上关闭第一晶体管。

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