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1. 发明申请

US20130342247A1 CAPACTIVE LOAD PLL WITH CALIBRATION LOOP 有权
标题翻译：具有校准环路的电容负载PLL
公开(公告)号：US20130342247A1
公开(公告)日：2013-12-26
申请号：US13530136
申请日：2012-06-22
申请人： Chan-Hong CHERN , Tao Wen CHUNG , Ming-Chieh HUANG , Chih-Chang LIN , Tsung-Ching HUANG , Fu-Lung HSUEH
发明人： Chan-Hong CHERN , Tao Wen CHUNG , Ming-Chieh HUANG , Chih-Chang LIN , Tsung-Ching HUANG , Fu-Lung HSUEH
IPC分类号： H03L7/08
CPC分类号： H03L7/103 , H03L7/097 , H03L7/0995 , H03L7/1072 , H03L7/18 , H03L2207/06
摘要： A circuit includes a capacitive-load voltage controlled oscillator having an input configured to receive a first input signal and an output configured to output an oscillating output signal. A calibration circuit is coupled to the voltage controlled oscillator and is configured to output one or more control signals to the capacitive-load voltage controlled oscillator for adjusting a frequency of the oscillating output signal. The calibration circuit is configured to output the one or more control signals in response to a comparison of an input voltage to at least one reference voltage.
摘要翻译：电路包括电容负载压控振荡器，其具有被配置为接收第一输入信号的输入和被配置为输出振荡输出信号的输出。校准电路耦合到压控振荡器，并被配置为将一个或多个控制信号输出到电容负载压控振荡器，用于调整振荡输出信号的频率。校准电路被配置为响应于输入电压与至少一个参考电压的比较而输出一个或多个控制信号。

2. 发明申请

US20130082754A1 PHASE LOCKED LOOP CALIBRATION 有权
标题翻译：相位锁定校准
公开(公告)号：US20130082754A1
公开(公告)日：2013-04-04
申请号：US13252498
申请日：2011-10-04
申请人： Chan-Hong CHERN , Ming-Chieh HUANG , Tao Wen CHUNG , Chih-Chang LIN , Fu-Lung HSUEH , Yuwen SWEI
发明人： Chan-Hong CHERN , Ming-Chieh HUANG , Tao Wen CHUNG , Chih-Chang LIN , Fu-Lung HSUEH , Yuwen SWEI
IPC分类号： H03L7/08
CPC分类号： H03L7/102 , H03L7/099 , H03L2207/06
摘要： An inductor-capacitor phase locked loop (LCPLL) includes an inductor-capacitor voltage controlled oscillator (LCVCO) that provides an output frequency. A calibration circuit includes two comparators and provides a coarse tune signal to the LCVCO. The two comparators respectively compare the loop filter signal with a first reference voltage and a second reference voltage that is higher than the first reference voltage to supply a first and second comparator output, respectively. The calibration circuit is capable of adjusting the coarse tune signal continuously in voltage values and adjusts the coarse tune signal based on the two comparator outputs. A loop filter provides a loop filter signal to the calibration circuit and a fine tune signal to the LCVCO. A coarse tune frequency range is greater than a fine tune frequency range.
摘要翻译：电感 - 电容器锁相环（LCPLL）包括提供输出频率的电感 - 电容压控振荡器（LCVCO）。校准电路包括两个比较器，并向LCVCO提供粗调信号。两个比较器分别将环路滤波器信号与第一参考电压和高于第一参考电压的第二参考电压进行比较，以分别提供第一和第二比较器输出。校准电路能够在电压值中连续调整粗调信号，并根据两个比较器输出调整粗调信号。环路滤波器向校准电路提供环路滤波器信号，并向LCVCO提供微调信号。粗调频率范围大于微调频率范围。

3. 发明申请

US20120230457A1 CLOCK AND DATA RECOVERY USING LC VOLTAGE CONTROLLED OSCILLATOR AND DELAY LOCKED LOOP 有权
标题翻译：使用LC电压控制振荡器和延迟锁定环路的时钟和数据恢复
公开(公告)号：US20120230457A1
公开(公告)日：2012-09-13
申请号：US13045788
申请日：2011-03-11
申请人： Chan-Hong CHERN , Chih-Chang LIN , Ming-Chieh HUANG , Fu-Lung HSUEH
发明人： Chan-Hong CHERN , Chih-Chang LIN , Ming-Chieh HUANG , Fu-Lung HSUEH
IPC分类号： H04L7/00
CPC分类号： H04L7/033 , H03L7/0807 , H03L7/081 , H03L7/113 , H04L7/0337
摘要： A clock and data recovery (CDR) circuit includes an inductor-capacitor voltage controlled oscillator (LCVCO) configured to generate a clock signal with a clock frequency. A delay locked loop (DLL) is configured to receive the clock signal from the LCVCO and generate multiple clock phases. A charge pump is configured to control the LCVCO. A phase detector is configured to receive a data input and the multiple clock phases from the DLL, and to control the first charge pump in order to align a data edge of the data input and the multiple clock phases.
摘要翻译：时钟和数据恢复（CDR）电路包括被配置为产生具有时钟频率的时钟信号的电感器 - 电容器压控振荡器（LCVCO）。延迟锁定环（DLL）被配置为从LCVCO接收时钟信号并生成多个时钟相位。电荷泵配置为控制LCVCO。相位检测器被配置为从DLL接收数据输入和多个时钟相位，并且控制第一电荷泵以便对准数据输入和多个时钟相位的数据沿。

4. 发明申请

US20120044008A1 LEVEL SHIFTERS FOR IO INTERFACES 有权
标题翻译： IO接口的水平移位器
公开(公告)号：US20120044008A1
公开(公告)日：2012-02-23
申请号：US12859456
申请日：2010-08-19
申请人： Chan-Hong CHERN , Fu-Lung HSUEH , Chih-Chang LIN , Yuwen SWEI , Ming-Chieh HUANG
发明人： Chan-Hong CHERN , Fu-Lung HSUEH , Chih-Chang LIN , Yuwen SWEI , Ming-Chieh HUANG
IPC分类号： H03L5/00
CPC分类号： H03K3/02 , H03K19/018521 , H03K19/018528
摘要： A level shifter includes an input node, an output node, a pull-up transistor, a pull-down transistor, and at least one diode-connected device coupled between the pull-up transistor and the pull-down transistor. The level shifter is arranged to be coupled to a high power supply voltage, to receive an input signal having a first voltage level at the input node, and to supply an output signal having a second voltage level at the output node. The high power supply voltage is higher than the first voltage level. The at least one diode-connected device allows the output signal to be pulled up to about a first diode voltage drop below the high power supply voltage and/or to be pulled down to about a second diode voltage drop above ground. The first diode voltage drop and the second diode voltage drop are from the at least one diode-connected device.
摘要翻译：电平移位器包括输入节点，输出节点，上拉晶体管，下拉晶体管以及耦合在上拉晶体管和下拉晶体管之间的至少一个二极管连接器件。电平移位器被布置为耦合到高电源电压，以在输入节点处接收具有第一电压电平的输入信号，并且在输出节点处提供具有第二电压电平的输出信号。高电源电压高于第一电压电平。所述至少一个二极管连接的装置允许输出信号被上拉到大约低于高电源电压的第一二极管电压降和/或被下拉到大约地面上的第二二极管电压降。第一二极管电压降和第二二极管压降来自至少一个二极管连接的器件。

5. 发明申请

US20120019302A1 LOW MINIMUM POWER SUPPLY VOLTAGE LEVEL SHIFTER 有权
标题翻译：低最低电源电压水平变换器
公开(公告)号：US20120019302A1
公开(公告)日：2012-01-26
申请号：US12843479
申请日：2010-07-26
申请人： Chan-Hong CHERN , Fu-Lung HSUEH , Ming-Chieh HUANG , Chih-Chang LIN
发明人： Chan-Hong CHERN , Fu-Lung HSUEH , Ming-Chieh HUANG , Chih-Chang LIN
IPC分类号： H03L5/00
CPC分类号： H03K19/018521
摘要： A level shifter includes one PMOS and two NMOS transistors. A source of the first NMOS transistor is coupled to a low power supply voltage. An input signal is coupled to a gate of the first NMOS transistor and a source of the second NMOS transistor. The input signal has a voltage level up to a first power supply voltage. A source of the PMOS transistor is coupled to a second power supply voltage, higher than the first power supply voltage. An output signal is coupled between the PMOS and the first NMOS transistors. The first NMOS transistor is arranged to pull down the output signal when the input signal is a logical 1, and the second NMOS transistor is arranged to enable the PMOS transistor to pull up the output signal to a logical 1 at the second power supply voltage when the input signal is a logical 0.
摘要翻译：电平移位器包括一个PMOS和两个NMOS晶体管。第一NMOS晶体管的源极耦合到低电源电压。输入信号耦合到第一NMOS晶体管的栅极和第二NMOS晶体管的源极。输入信号具有高达第一电源电压的电压电平。 PMOS晶体管的源极耦合到高于第一电源电压的第二电源电压。输出信号耦合在PMOS和第一NMOS晶体管之间。第一NMOS晶体管被布置为当输入信号为逻辑1时下拉输出信号，并且第二NMOS晶体管被布置为使得PMOS晶体管能够以第二电源电压将输出信号上拉至逻辑1，输入信号为逻辑0。

6. 发明申请

US20110267107A1 CIRCUIT FOR REDUCING NEGATIVE BIAS TEMPERATURE INSTABILITY 有权
标题翻译：减少负偏差温度不稳定性的电路
公开(公告)号：US20110267107A1
公开(公告)日：2011-11-03
申请号：US12768899
申请日：2010-04-28
申请人： Chan-Hong CHERN , Fu-Lung HSUEH , Ming-Chieh HUANG , Bryan SHEFFIELD , Chih-Chang LIN
发明人： Chan-Hong CHERN , Fu-Lung HSUEH , Ming-Chieh HUANG , Bryan SHEFFIELD , Chih-Chang LIN
IPC分类号： H03K19/094 , H03K19/096
CPC分类号： H03K19/01855 , H03K3/012 , H03K3/356008 , H03K3/35625 , H03K19/0016 , H03K19/0963
摘要： A circuit includes an operational PMOS transistor of a logic gate driver. A control circuit is configured to turn off the operational PMOS transistor during a standby mode. The circuit also includes a sacrificial PMOS transistor coupled to an output node. The operational PMOS transistor is coupled to the output node. The sacrificial PMOS transistor is configured to keep the output node at a logical 1 during the standby mode.
摘要翻译：电路包括逻辑门驱动器的操作PMOS晶体管。控制电路被配置为在待机模式期间关闭操作PMOS晶体管。电路还包括耦合到输出节点的牺牲PMOS晶体管。操作PMOS晶体管耦合到输出节点。牺牲PMOS晶体管被配置为在待机模式期间将输出节点保持在逻辑1。

7. 发明申请

US20120050930A1 VOL UP-SHIFTING LEVEL SHIFTERS 有权
公开(公告)号：US20120050930A1
公开(公告)日：2012-03-01
申请号：US12871343
申请日：2010-08-30
申请人： Chan-Hong CHERN , Fu-Lung HSUEH , Yuwen SWEI , Chih-Chang LIN
发明人： Chan-Hong CHERN , Fu-Lung HSUEH , Yuwen SWEI , Chih-Chang LIN
IPC分类号： H02H9/04 , H03L5/00
CPC分类号： H03K19/0941 , H03K3/356182 , H03K19/018514
摘要： A representative level-shifter comprises a dynamically biased current source circuit that receives a first voltage, a first and a second unidirectional current-conducting devices, a first and a second pull-down devices, and a pull-up device. The first and second unidirectional current-conducting devices are coupled to the dynamically biased current source circuit. A voltage output of the level-shifter is located at a first node that is located between the current-constant circuit and the second unidirectional current-conducting device. The first and second pull-down devices are coupled to the first and second unidirectional current-conducting devices, respectively. The pull-up device receives a second voltage and is coupled to the dynamically biased current source circuit and the first unidirectional current-conducting device. The pull-up device is configured to dynamically bias the dynamically biased current source circuit such that a voltage drop of the second unidirectional current-conducting device is output at the voltage output responsive to the pull-up device outputting the second voltage to the dynamically biased current source circuit, the first pull-down device being non-conducting and the second pull-down device being conducting.
摘要翻译：代表性的电平转换器包括接收第一电压，第一和第二单向导流器件，第一和第二下拉器件以及上拉器件的动态偏置电流源电路。第一和第二单向导流器件耦合到动态偏置电流源电路。电平移位器的电压输出位于位于电流恒定电路和第二单向导流器件之间的第一节点处。第一和第二下拉装置分别耦合到第一和第二单向导流装置。上拉装置接收第二电压并耦合到动态偏置电流源电路和第一单向导流装置。上拉装置被配置为动态地偏置动态偏置的电流源电路，使得第二单向导流装置的电压降在电压输出处被输出，响应于上拉装置将第二电压输出到动态偏置电流源电路，第一下拉装置不导通，第二下拉装置导通。

8. 发明申请

US20120266126A1 SYSTEMS AND METHODS OF DESIGNING INTEGRATED CIRCUITS 有权
标题翻译：设计集成电路的系统与方法
公开(公告)号：US20120266126A1
公开(公告)日：2012-10-18
申请号：US13084748
申请日：2011-04-12
申请人： Chan-Hong CHERN , Fu-Lung HSUEH , Li-Chun TIEN
发明人： Chan-Hong CHERN , Fu-Lung HSUEH , Li-Chun TIEN
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： A method of designing an integrated circuit includes providing a cell library including a first and second cell structures. The cell structures each include a dummy gate electrode disposed on a boundary. An edge gate electrode is disposed adjacent to the dummy gate electrode. An oxide definition (OD) region has an edge disposed between the edge gate electrode and the dummy gate electrode. The method includes determining if the cell structures are to be abutted with each other. If so, the method includes abutting the cell structures. If not so, the method includes increasing areas of portions of the OD regions between the edge gate electrodes and the dummy gate electrodes.
摘要翻译：设计集成电路的方法包括提供包括第一和第二单元结构的单元库。电池结构各自包括设置在边界上的虚拟栅电极。边缘栅电极被设置成与虚拟栅电极相邻。氧化物定义（OD）区域具有设置在边缘栅电极和伪栅电极之间的边缘。该方法包括确定单元结构是否彼此邻接。如果是，则该方法包括邻接单元结构。如果不是这样，则该方法包括增加边缘栅极电极和虚拟栅电极之间的OD区域的部分区域。

9. 发明申请

US20130126979A1 INTEGRATED CIRCUITS WITH ELECTRICAL FUSES AND METHODS OF FORMING THE SAME 有权
标题翻译：具有电熔丝的集成电路及其形成方法
公开(公告)号：US20130126979A1
公开(公告)日：2013-05-23
申请号：US13302335
申请日：2011-11-22
申请人： Chan-Hong CHERN , Fu-Lung HSUEH , Kuoyuan (Peter) HSU
发明人： Chan-Hong CHERN , Fu-Lung HSUEH , Kuoyuan (Peter) HSU
IPC分类号： H01L27/13 , H01L21/02
CPC分类号： H01L23/5256 , H01L21/823437 , H01L27/0617 , H01L27/0629 , H01L27/11206 , H01L29/4966 , H01L29/517 , H01L29/66545 , H01L2924/0002 , H01L2924/00
摘要： A method of forming an integrated circuit includes forming at least one transistor over a substrate. Forming the at least one transistor includes forming a gate dielectric structure over a substrate. A work-function metallic layer is formed over the gate dielectric structure. A conductive layer is formed over the work-function metallic layer. A source/drain (S/D) region is formed adjacent to each sidewall of the gate dielectric structure. At least one electrical fuse is formed over the substrate. Forming the at least one electrical fuse includes forming a first semiconductor layer over the substrate. A first silicide layer is formed on the first semiconductor layer.
摘要翻译：形成集成电路的方法包括在衬底上形成至少一个晶体管。形成至少一个晶体管包括在衬底上形成栅极电介质结构。在栅介电结构上形成功函数金属层。在功函数金属层上形成导电层。源极/漏极（S / D）区域形成为与栅极电介质结构的每个侧壁相邻。在衬底上形成至少一个电熔丝。形成至少一个电熔丝包括在衬底上形成第一半导体层。在第一半导体层上形成第一硅化物层。

10. 发明申请

US20120217586A1 INTEGRATED CIRCUITS WITH RESISTORS AND METHODS OF FORMING THE SAME 有权
标题翻译：具有电阻的集成电路及其形成方法
公开(公告)号：US20120217586A1
公开(公告)日：2012-08-30
申请号：US13035533
申请日：2011-02-25
申请人： Chan-Hong CHERN , Fu-Lung HSUEH
发明人： Chan-Hong CHERN , Fu-Lung HSUEH
IPC分类号： H01L27/06 , H01L21/8234
CPC分类号： H01L27/0629 , H01L27/1207 , H01L28/20 , H01L29/42364 , H01L29/42372 , H01L29/4958 , H01L29/4966 , H01L29/4975
摘要： A method of forming an integrated circuit includes forming at least one transistor over a substrate. The at least one transistor includes a first gate dielectric structure disposed over a substrate. A work-function metallic layer is disposed over the first gate dielectric structure. A conductive layer is disposed over the work-function metallic layer. A source/drain (S/D) region is disposed adjacent to each sidewall of the first gate dielectric structure. At least one resistor structure is formed over the substrate. The at least one resistor structure includes a first doped semiconductor layer disposed over the substrate. The at least one resistor structure does not include any work-function metallic layer between the first doped semiconductor layer and the substrate.
摘要翻译：形成集成电路的方法包括在衬底上形成至少一个晶体管。所述至少一个晶体管包括设置在衬底上的第一栅极电介质结构。工作功能金属层设置在第一栅极电介质结构上。导电层设置在功函数金属层上。源极/漏极（S / D）区域邻近第一栅极电介质结构的每个侧壁设置。在衬底上形成至少一个电阻器结构。所述至少一个电阻器结构包括设置在所述衬底上的第一掺杂半导体层。至少一个电阻器结构不包括在第一掺杂半导体层和衬底之间的任何功函数金属层。

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