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1. 发明授权

US08006210B2 Logic transformation and gate placement to avoid routing congestion 有权
标题翻译：逻辑转换和门放置，以避免路由拥塞
公开(公告)号：US08006210B2
公开(公告)日：2011-08-23
申请号：US12014344
申请日：2008-01-15
申请人： Chaitra M. Bhat , Chandrika Madhwacharya , Atsushi Sugai , Toshihiko Yokota
发明人： Chaitra M. Bhat , Chandrika Madhwacharya , Atsushi Sugai , Toshihiko Yokota
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： A novel logic design method for avoiding wiring congestion. According to the novel logic design method, an original gate having multiple inputs coming from different directions and having multiple outputs coming to different directions can be transformed to a logic block that has an input stage and an output stage. The gates of the input stage receive signals from the multiple inputs of the original gate. The gates of the output stage send signals to the multiple outputs of the original gate. Each gate of the input stage is placed in a vicinity of its inputs. Each gate of the output stage is placed in a vicinity of its outputs. The gates of the input and output stages are functionally equivalent to the original gate.
摘要翻译：一种避免布线堵塞的新颖逻辑设计方法。根据新颖的逻辑设计方法，可以将具有来自不同方向的多个输入并且具有进入不同方向的多个输出的原始门转换为具有输入级和输出级的逻辑块。输入级的门从原始门的多个输入接收信号。输出级的门将信号发送到原始门的多个输出。输入级的每个门都放置在其输入端附近。输出级的每个门都放置在其输出端附近。输入和输出级的门在功能上等同于原始门。

2. 发明授权

US08161445B2 Logic transformation and gate placement to avoid routing congestion 有权
标题翻译：逻辑转换和门放置，以避免路由拥塞
公开(公告)号：US08161445B2
公开(公告)日：2012-04-17
申请号：US12015631
申请日：2008-01-17
申请人： Chaitra M. Bhat , Chandrika Madhwacharya , Atsushi Sugai , Toshihiko Yokota
发明人： Chaitra M. Bhat , Chandrika Madhwacharya , Atsushi Sugai , Toshihiko Yokota
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： A novel logic design method for avoiding wiring congestion. According to the novel logic design method, an original gate having multiple inputs coming from different directions and having multiple outputs coming to different directions can be transformed to a logic block that has an input stage and an output stage. The gates of the input stage receive signals from the multiple inputs of the original gate. The gates of the output stage send signals to the multiple outputs of the original gate. Each gate of the input stage is placed in a vicinity of its inputs. Each gate of the output stage is placed in a vicinity of its outputs. The gates of the input and output stages are functionally equivalent to the original gate.
摘要翻译：一种避免布线堵塞的新颖逻辑设计方法。根据新颖的逻辑设计方法，可以将具有来自不同方向的多个输入并且具有进入不同方向的多个输出的原始门转换为具有输入级和输出级的逻辑块。输入级的门从原始门的多个输入接收信号。输出级的门将信号发送到原始门的多个输出。输入级的每个门都放置在其输入端附近。输出级的每个门都放置在其输出端附近。输入和输出级的门在功能上等同于原始门。

3. 发明申请

US20080134110A1 LOGIC TRANSFORMATION AND GATE PLACEMENT TO AVOID ROUTING CONGESTION 有权
公开(公告)号：US20080134110A1
公开(公告)日：2008-06-05
申请号：US12015631
申请日：2008-01-17
申请人： Chaitra M. Bhat , M. Chandrika , Atsushi Sugai , Toshihiko Yokota
发明人： Chaitra M. Bhat , M. Chandrika , Atsushi Sugai , Toshihiko Yokota
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： A novel logic design method for avoiding wiring congestion. According to the novel logic design method, an original gate having multiple inputs coming from different directions and having multiple outputs coming to different directions can be transformed to a logic block that has an input stage and an output stage. The gates of the input stage receive signals from the multiple inputs of the original gate. The gates of the output stage send signals to the multiple outputs of the original gate. Each gate of the input stage is placed in a vicinity of its inputs. Each gate of the output stage is placed in a vicinity of its outputs. The gates of the input and output stages are functionally equivalent to the original gate.

4. 发明授权

US07356797B2 Logic transformation and gate placement to avoid routing congestion 有权
标题翻译：逻辑转换和门放置，以避免路由拥塞
公开(公告)号：US07356797B2
公开(公告)日：2008-04-08
申请号：US11153707
申请日：2005-06-14
申请人： Chaitra M. Bhat , M. Chandrika , Atsushi Sugai , Toshihiko Yokota
发明人： Chaitra M. Bhat , M. Chandrika , Atsushi Sugai , Toshihiko Yokota
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： A novel logic design method for avoiding wiring congestion. According to the novel logic design method, an original gate having multiple inputs coming from different directions and having multiple outputs coming to different directions can be transformed to a logic block that has an input stage and an output stage. The gates of the input stage receive signals from the multiple inputs of the original gate. The gates of the output stage send signals to the multiple outputs of the original gate. Each gate of the input stage is placed in a vicinity of its inputs. Each gate of the output stage is placed in a vicinity of its outputs. The gates of the input and output stages are functionally equivalent to the original gate.
摘要翻译：一种避免布线堵塞的新颖逻辑设计方法。根据新颖的逻辑设计方法，可以将具有来自不同方向的多个输入并且具有进入不同方向的多个输出的原始门转换为具有输入级和输出级的逻辑块。输入级的门从原始门的多个输入接收信号。输出级的门将信号发送到原始门的多个输出。输入级的每个门都放置在其输入端附近。输出级的每个门都放置在其输出端附近。输入和输出级的门在功能上等同于原始门。

5. 发明申请

US20080115094A1 LOGIC TRANSFORMATION AND GATE PLACEMENT TO AVOID ROUTING CONGESTION 有权
标题翻译：逻辑转换和栅格放置避免路由约束
公开(公告)号：US20080115094A1
公开(公告)日：2008-05-15
申请号：US12014344
申请日：2008-01-15
申请人： Chaitra Bhat , M. Chandrika , Atsushi Sugai , Toshihiko Yokota
发明人： Chaitra Bhat , M. Chandrika , Atsushi Sugai , Toshihiko Yokota
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： A novel logic design method for avoiding wiring congestion. According to the novel logic design method, an original gate having multiple inputs coming from different directions and having multiple outputs coming to different directions can be transformed to a logic block that has an input stage and an output stage. The gates of the input stage receive signals from the multiple inputs of the original gate. The gates of the output stage send signals to the multiple outputs of the original gate. Each gate of the input stage is placed in a vicinity of its inputs. Each gate of the output stage is placed in a vicinity of its outputs. The gates of the input and output stages are functionally equivalent to the original gate.
摘要翻译：一种避免布线堵塞的新颖逻辑设计方法。根据新颖的逻辑设计方法，可以将具有来自不同方向的多个输入并且具有进入不同方向的多个输出的原始门转换为具有输入级和输出级的逻辑块。输入级的门从原始门的多个输入接收信号。输出级的门将信号发送到原始门的多个输出。输入级的每个门都放置在其输入端附近。输出级的每个门都放置在其输出端附近。输入和输出级的门在功能上等同于原始门。

6. 发明申请

US20060282809A1 Logic transformation and gate placement to avoid routing congestion 有权
标题翻译：逻辑转换和门放置，以避免路由拥塞
公开(公告)号：US20060282809A1
公开(公告)日：2006-12-14
申请号：US11153707
申请日：2005-06-14
申请人： Chaitra Bhat , M. Chandrika , Atsushi Sugai , Toshihiko Yokota
发明人： Chaitra Bhat , M. Chandrika , Atsushi Sugai , Toshihiko Yokota
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： A novel logic design method for avoiding wiring congestion. According to the novel logic design method, an original gate having multiple inputs coming from different directions and having multiple outputs coming to different directions can be transformed to a logic block that has an input stage and an output stage. The gates of the input stage receive signals from the multiple inputs of the original gate. The gates of the output stage send signals to the multiple outputs of the original gate. Each gate of the input stage is placed in a vicinity of its inputs. Each gate of the output stage is placed in a vicinity of its outputs. The gates of the input and output stages are functionally equivalent to the original gate.
摘要翻译：一种避免布线堵塞的新颖逻辑设计方法。根据新颖的逻辑设计方法，可以将具有来自不同方向的多个输入并且具有进入不同方向的多个输出的原始门转换为具有输入级和输出级的逻辑块。输入级的门从原始门的多个输入接收信号。输出级的门将信号发送到原始门的多个输出。输入级的每个门都放置在其输入端附近。输出级的每个门都放置在其输出端附近。输入和输出级的门在功能上等同于原始门。

7. 发明申请

US20080209292A1 CIRCUIT FOR CONTROLLING VOLTAGE FLUCTUATION IN INTEGRATED CIRCUIT 失效
标题翻译：用于控制集成电路中电压波动的电路
公开(公告)号：US20080209292A1
公开(公告)日：2008-08-28
申请号：US12035536
申请日：2008-02-22
申请人： Toshihiko Yokota
发明人： Toshihiko Yokota
IPC分类号： G01R31/3187
CPC分类号： G01R31/318594
摘要： An integrated circuit and related method for controlling voltage fluctuations. The integrated circuit includes a plurality of clock buffers and a plurality of latches synchronously operated in accordance with operating clock signals distributed via the clock buffers. The circuit comprises a mechanism for performing an At Speed Test to shift data that are initially set for the latches in accordance with the operating clock signals to succeeding latches, respectively. It also has a timing designation circuit for generating a first output signal that is active for a period from a predetermined time, which is after the integrated circuit is powered on and before an operating clock signal for the At Speed Test is generated, to a time when the operating clock signal is generated. In addition, it also includes a current consumption circuit provided in correspondence with each of at least a part of the plurality of clock buffers, for consuming a certain amount of current in the period during which the first output signal is active.
摘要翻译：一种用于控制电压波动的集成电路及相关方法。集成电路包括多个时钟缓冲器和多个锁存器，这些锁存器根据经由时钟缓冲器分配的操作时钟信号同步操作。该电路包括用于执行At Speed测试以分别将根据操作时钟信号将锁存器初始设置的数据移位到后续锁存器的机构。它还具有一个时序指定电路，用于产生一个第一输出信号，该第一输出信号在从集成电路上电之后的预定时间起，并且在产生用于速度测试的操作时钟信号之前的一段时间内被激活一段时间当产生操作时钟信号时。此外，它还包括与多个时钟缓冲器的至少一部分中的每一个相对应地设置的用于在第一输出信号有效的时段内消耗一定量的电流的电流消耗电路。

8. 发明申请

US20070198882A1 METHOD AND CIRCUIT FOR LSSD TESTING 失效
标题翻译： LSSD测试方法与电路
公开(公告)号：US20070198882A1
公开(公告)日：2007-08-23
申请号：US11672072
申请日：2007-02-07
申请人： Ken Namura , Sanae Seike , Toshihiko Yokota
发明人： Ken Namura , Sanae Seike , Toshihiko Yokota
IPC分类号： G01R31/28
CPC分类号： G01R31/31725 , G01R31/31726 , G01R31/318594
摘要： A method and integrated circuit for LSSD testing. The integrated circuit includes a plurality of clock domains supplied with test clocks from separate clock generation circuits. In each clock domain, a scan latch at a clock domain boundary receiving an input from another clock domain includes a master latch for latching an input in response to a first clock, a slave latch for latching an output from the master latch in response to a second clock, a selector for supplying the master latch with a system input when the mode selection signal is at a second level, and a clock control circuit for turning off the first clock when the mode selection signal transits from the first level to the second level.
摘要翻译：一种用于LSSD测试的方法和集成电路。集成电路包括从单独的时钟发生电路提供有测试时钟的多个时钟域。在每个时钟域中，在接收来自另一时钟域的输入的时钟域边界处的扫描锁存器包括用于响应于第一时钟锁存输入的主锁存器，用于响应于主器件锁存来自主锁存器的输出的从锁存器第二时钟，当模式选择信号处于第二电平时，用于向主锁存器提供系统输入的选择器;以及当模式选择信号从第一电平转换到第二电平时关闭第一时钟的时钟控制电路。

9. 发明授权

US07752513B2 Method and circuit for LSSD testing 失效
标题翻译： LSSD测试方法和电路
公开(公告)号：US07752513B2
公开(公告)日：2010-07-06
申请号：US11672072
申请日：2007-02-07
申请人： Ken Namura , Sanae Seike , Toshihiko Yokota
发明人： Ken Namura , Sanae Seike , Toshihiko Yokota
IPC分类号： G01R31/28
CPC分类号： G01R31/31725 , G01R31/31726 , G01R31/318594
摘要： A method and integrated circuit for LSSD testing. The integrated circuit includes a plurality of clock domains supplied with test clocks from separate clock generation circuits. In each clock domain, a scan latch at a clock domain boundary receiving an input from another clock domain includes a master latch for latching an input in response to a first clock, a slave latch for latching an output from the master latch in response to a second clock, a selector for supplying the master latch with a system input when the mode selection signal is at a second level, and a clock control circuit for turning off the first clock when the mode selection signal transits from the first level to the second level.
摘要翻译：一种用于LSSD测试的方法和集成电路。集成电路包括从单独的时钟发生电路提供有测试时钟的多个时钟域。在每个时钟域中，在接收来自另一时钟域的输入的时钟域边界处的扫描锁存器包括用于响应于第一时钟锁存输入的主锁存器，用于响应于主器件锁存来自主锁存器的输出的从锁存器第二时钟，当模式选择信号处于第二电平时，用于向主锁存器提供系统输入的选择器;以及当模式选择信号从第一电平转换到第二电平时关闭第一时钟的时钟控制电路。

10. 发明申请

US20090119561A1 Microcomputer and Method of Testing The Same 失效
标题翻译：微电脑及其测试方法
公开(公告)号：US20090119561A1
公开(公告)日：2009-05-07
申请号：US11916702
申请日：2006-06-08
申请人： Toshihiko Yokota , Ken Namura , Mitsuru Sugimoto
发明人： Toshihiko Yokota , Ken Namura , Mitsuru Sugimoto
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G01R31/2812 , G01R31/2815 , G01R31/31855
摘要： Embodiments of the present invention provide a microcomputer on which a plurality of ICs (Integrated Circuits) connected from one another by a source-synchronous interface is mounted. The microcomputer includes an IC on the side for transmitting data through the source-synchronous interface which further includes: a PLL (Phase-Locked Loop) circuit being adapted for transmitting an operation clock in actual operation; a first flip-flop being adapted for transmitting test data in accordance with the operation clock transmitted from the PLL circuit; and a second flip-flop being adapted for transmitting a synchronous clock in source-synchronous, in accordance with the operation clock transmitted from the PLL circuit, a synchronous clock in source synchronous, and an IC on the side for receiving data through the source-synchronous interface which further includes a third flip-flop being adapted for capturing, in accordance with the synchronous clock transmitted from the second flip-flop, the test data transmitted from the first flip-flop. Methods for testing the microcomputer are also provided.
摘要翻译：本发明的实施例提供了一种微型计算机，其上安装有通过源同步接口彼此连接的多个IC（集成电路）。微型计算机包括：一侧的IC，用于通过源同步接口发送数据，该IC进一步包括：PLL（锁相环）电路，适于在实际操作中发送操作时钟; 第一触发器适于根据从PLL电路发送的操作时钟发送测试数据; 以及第二触发器，其适于根据从PLL电路发送的操作时钟，源同步的同步时钟和用于通过源极同步的接收数据的一侧的IC发送源同步的同步时钟，同步接口还包括第三触发器，其适于根据从第二触发器发送的同步时钟从第一触发器发送的测试数据进行捕获。还提供了测试微型计算机的方法。

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