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1. 发明申请

US20050269648A1 Gated field effect devices 有权
标题翻译：门控场效应器件
公开(公告)号：US20050269648A1
公开(公告)日：2005-12-08
申请号：US10861744
申请日：2004-06-04
申请人： Cem Basceri , H. Montgomery Manning , Gurtej Sandhu , Kunal Parekh
发明人： Cem Basceri , H. Montgomery Manning , Gurtej Sandhu , Kunal Parekh
IPC分类号： H01L21/28 , H01L29/49 , H01L29/51 , H01L29/76 , H01L21/336
CPC分类号： H01L29/4983 , H01L21/28194 , H01L29/512 , H01L29/517
摘要： This invention includes gated field effect devices, and methods of forming gated field effect devices. In one implementation, a gated field effect device includes a pair of source/drain regions having a channel region therebetween. A gate is received proximate the channel region between the source/drain regions. The gate has a gate width between the source/drain regions. A gate dielectric is received intermediate the channel region and the gate. The gate dielectric has at least two different regions along the width of the gate. The different regions are characterized by different materials which are effective to define the two different regions to have different dielectric constants k. Other aspects and implementations are contemplated.
摘要翻译：本发明包括门控场效应器件，以及形成门控场效应器件的方法。在一种实施方案中，门控场效应器件包括在其间具有沟道区的一对源/漏区。在源极/漏极区域之间的沟道区域附近接收栅极。栅极在源极/漏极区之间具有栅极宽度。栅极电介质被接收在沟道区域和栅极之间。栅极电介质沿着栅极的宽度具有至少两个不同的区域。不同的区域由不同的材料表征，其有效地限定两个不同的区域以具有不同的介电常数k。考虑了其他方面和实现。

2. 发明申请

US20060258087A1 Methods of forming vertical transistor structures 有权
公开(公告)号：US20060258087A1
公开(公告)日：2006-11-16
申请号：US11486524
申请日：2006-07-13
申请人： H. Manning , Kunal Parekh , Cem Basceri , Gurtej Sandhu
发明人： H. Manning , Kunal Parekh , Cem Basceri , Gurtej Sandhu
IPC分类号： H01L21/8242 , H01L21/336 , H01L21/425 , H01L21/8238
CPC分类号： H01L29/66787 , H01L27/10808 , H01L27/10876
摘要： The invention includes methods in which an angled implant is utilized to self-align a source/drain region implant with the top edge of a gateline of a vertical transistor structure. The invention also includes methods in which an angled implant is utilized to implant dopant beneath the gateline of a vertical transistor structure. Vertical transistor structures formed in accordance with methodology of the present invention can be incorporated into various types of integrated circuitry, including, for example, DRAM arrays.

3. 发明申请

US20060001072A1 Methods of forming a gated device 有权
标题翻译：形成门控装置的方法
公开(公告)号：US20060001072A1
公开(公告)日：2006-01-05
申请号：US11171873
申请日：2005-06-30
申请人： Cem Basceri , H. Manning , Gurtej Sandhu , Kunal Parekh
发明人： Cem Basceri , H. Manning , Gurtej Sandhu , Kunal Parekh
IPC分类号： H01L21/8238 , H01L27/108 , H01L29/792
CPC分类号： H01L29/4983 , H01L21/28194 , H01L29/512 , H01L29/517
摘要： This invention includes gated field effect devices, and methods of forming gated field effect devices. In one implementation, a gated field effect device includes a pair of source/drain regions having a channel region therebetween. A gate is received proximate the channel region between the source/drain regions. The gate has a gate width between the source/drain regions. A gate dielectric is received intermediate the channel region and the gate. The gate dielectric has at least two different regions along the width of the gate. The different regions are characterized by different materials which are effective to define the two different regions to have different dielectric constants k. Other aspects and implementations are contemplated.
摘要翻译：本发明包括门控场效应器件，以及形成门控场效应器件的方法。在一种实施方案中，门控场效应器件包括在其间具有沟道区的一对源/漏区。在源极/漏极区域之间的沟道区域附近接收栅极。栅极在源极/漏极区之间具有栅极宽度。栅极电介质被接收在沟道区域和栅极之间。栅极电介质沿着栅极的宽度具有至少两个不同的区域。不同的区域由不同的材料表征，其有效地限定两个不同的区域以具有不同的介电常数k。考虑了其他方面和实现。

4. 发明申请

US20060046392A1 Methods of forming vertical transistor structures 审中-公开
标题翻译：形成垂直晶体管结构的方法
公开(公告)号：US20060046392A1
公开(公告)日：2006-03-02
申请号：US10928467
申请日：2004-08-26
申请人： H. Manning , Kunal Parekh , Cem Basceri , Gurtej Sandhu
发明人： H. Manning , Kunal Parekh , Cem Basceri , Gurtej Sandhu
IPC分类号： H01L21/336 , H01L21/3205 , H01L21/425 , H01L21/8242
CPC分类号： H01L29/66787 , H01L27/10808 , H01L27/10876
摘要： The invention includes methods in which an angled implant is utilized to self-align a source/drain region implant with the top edge of a gateline of a vertical transistor structure. The invention also includes methods in which an angled implant is utilized to implant dopant beneath the gateline of a vertical transistor structure. Vertical transistor structures formed in accordance with methodology of the present invention can be incorporated into various types of integrated circuitry, including, for example, DRAM arrays.
摘要翻译：本发明包括这样的方法，其中使用成角度的注入来使源极/漏极区域注入与垂直晶体管结构的天线的顶部边缘自对准。本发明还包括其中使用成角度的植入物以在垂直晶体管结构的栅极下注入掺杂剂的方法。根据本发明的方法形成的垂直晶体管结构可以结合到各种类型的集成电路中，包括例如DRAM阵列。

5. 发明申请

US20060038244A1 Gated field effect devices 失效
标题翻译：门控场效应器件
公开(公告)号：US20060038244A1
公开(公告)日：2006-02-23
申请号：US11253461
申请日：2005-10-19
申请人： Cem Basceri , H. Manning , Gurtej Sandhu , Kunal Parekh
发明人： Cem Basceri , H. Manning , Gurtej Sandhu , Kunal Parekh
IPC分类号： H01L29/94
CPC分类号： H01L29/4983 , H01L21/28194 , H01L29/512 , H01L29/517
摘要： This invention includes gated field effect devices, and methods of forming gated field effect devices. In one implementation, a gated field effect device includes a pair of source/drain regions having a channel region therebetween. A gate is received proximate the channel region between the source/drain regions. The gate has a gate width between the source/drain regions. A gate dielectric is received intermediate the channel region and the gate. The gate dielectric has at least two different regions along the width of the gate. The different regions are characterized by different materials which are effective to define the two different regions to have different dielectric constants k. Other aspects and implementations are contemplated.
摘要翻译：本发明包括门控场效应器件，以及形成门控场效应器件的方法。在一种实施方案中，门控场效应器件包括在其间具有沟道区的一对源/漏区。在源极/漏极区域之间的沟道区域附近接收栅极。栅极在源极/漏极区之间具有栅极宽度。栅极电介质被接收在沟道区域和栅极之间。栅极电介质沿着栅极的宽度具有至少两个不同的区域。不同的区域由不同的材料表征，其有效地限定两个不同的区域以具有不同的介电常数k。考虑了其他方面和实现。

6. 发明申请

US20060258086A1 Methods of forming vertical transistor structures 有权
公开(公告)号：US20060258086A1
公开(公告)日：2006-11-16
申请号：US11486512
申请日：2006-07-13
申请人： H. Manning , Kunal Parekh , Cem Basceri , Gurtej Sandhu
发明人： H. Manning , Kunal Parekh , Cem Basceri , Gurtej Sandhu
IPC分类号： H01L21/8242 , H01L21/336 , H01L21/8238
CPC分类号： H01L29/66787 , H01L27/10808 , H01L27/10876
摘要： The invention includes methods in which an angled implant is utilized to self-align a source/drain region implant with the top edge of a gateline of a vertical transistor structure. The invention also includes methods in which an angled implant is utilized to implant dopant beneath the gateline of a vertical transistor structure. Vertical transistor structures formed in accordance with methodology of the present invention can be incorporated into various types of integrated circuitry, including, for example, DRAM arrays.

7. 发明申请

US20090127656A1 Dielectric relaxation memory 有权
标题翻译：介质松弛记忆
公开(公告)号：US20090127656A1
公开(公告)日：2009-05-21
申请号：US12289692
申请日：2008-10-31
申请人： Cem Basceri , Gurtej Sandhu
发明人： Cem Basceri , Gurtej Sandhu
IPC分类号： H01L29/00
CPC分类号： H01L27/1085
摘要： A capacitor structure having a dielectric layer disposed between two conductive electrodes, wherein the dielectric layer contains at least one charge trap site corresponding to a specific energy state. The energy states may be used to distinguish memory states for the capacitor structure, allowing the invention to be used as a memory device. A method of forming the trap cites involves an atomic layer deposition of a material at pre-determined areas in the dielectric layer.
摘要翻译：一种具有设置在两个导电电极之间的电介质层的电容器结构，其中所述电介质层包含对应于特定能量状态的至少一个电荷陷阱位置。能量状态可以用于区分电容器结构的存储器状态，从而允许本发明用作存储器件。形成陷阱的方法涉及在电介质层中的预定区域处的材料的原子层沉积。

8. 发明授权

US07388248B2 Dielectric relaxation memory 有权
标题翻译：介质松弛记忆
公开(公告)号：US07388248B2
公开(公告)日：2008-06-17
申请号：US10930774
申请日：2004-09-01
申请人： Cem Basceri , Gurtej Sandhu
发明人： Cem Basceri , Gurtej Sandhu
IPC分类号： H01L29/78 , H02H3/22
CPC分类号： H01L27/1085
摘要： A capacitor structure having a dielectric layer disposed between two conductive electrodes, wherein the dielectric layer contains at least one charge trap site corresponding to a specific energy state. The energy states may be used to distinguish memory states for the capacitor structure, allowing the invention to be used as a memory device. A method of forming the trap cites involves an atomic layer deposition,of a material at pre-determined areas in the dielectric layer.
摘要翻译：一种具有设置在两个导电电极之间的电介质层的电容器结构，其中所述电介质层包含对应于特定能量状态的至少一个电荷陷阱位置。能量状态可以用于区分电容器结构的存储器状态，从而允许本发明用作存储器件。形成陷阱的方法涉及在电介质层中预定区域处的材料的原子层沉积。

9. 发明申请

US20070069270A1 Top electrode in a strongly oxidizing environment 审中-公开
标题翻译：顶极电极处于强氧化环境
公开(公告)号：US20070069270A1
公开(公告)日：2007-03-29
申请号：US11398498
申请日：2006-04-04
申请人： Cem Basceri , Howard Rhodes , Gurtej Sandhu , F. Gealy , Thomas Graettinger
发明人： Cem Basceri , Howard Rhodes , Gurtej Sandhu , F. Gealy , Thomas Graettinger
IPC分类号： H01L29/94
CPC分类号： H01L28/65 , H01L21/31637 , H01L21/31691 , H01L23/5222 , H01L27/10852 , H01L28/56 , H01L28/60 , H01L2924/0002 , H01L2924/00
摘要： An improved charge storing device and methods for providing the same, the charge storing device comprising a conductor-insulator-conductor (CIC) sandwich. The CIC sandwich comprises a first conducting layer deposited on a semiconductor integrated circuit. The CIC sandwich further comprises a first insulating layer deposited over the first conducting layer in a flush manner. The first insulating layer comprises a structure having a plurality of oxygen cites and a plurality of oxygen atoms that partially fill the oxygen cites, wherein the unfilled oxygen cites define a concentration of oxygen vacancies. The CIC sandwich further comprises a second conducting layer deposited over the first insulating layer in a strongly oxidizing ambient so as to reduce the concentration of oxygen vacancies in the first insulating layer, so as to provide an oxygen-rich interface layer between the first insulating layer and the second conducting layer, and so as to trap a plurality of oxygen atoms within the second conducting layer. The oxygen-rich interface layer and second conducting layer act as oxygen vacancy sinks for absorbing migrating oxygen vacancies that originate from the first insulating layer to thereby reduce the concentration of oxygen vacancies in the first insulating layer and to thereby reduce the buildup of oxygen vacancies at the interface layer. Thus, the first insulating layer provides an increased dielectric constant and an increased resistance to current flowing therethrough so as to increase the capacitance of the CIC sandwich and so as to reduce leakage currents flowing through the CIC sandwich.
摘要翻译：一种改进的电荷存储装置及其提供方法，电荷存储装置包括导体 - 绝缘体导体（CIC）三明治。 CIC夹层包括沉积在半导体集成电路上的第一导电层。 CIC夹层还包括以齐平方式沉积在第一导电层上的第一绝缘层。第一绝缘层包括具有多个氧化物和部分填充氧化物的多个氧原子的结构，其中未填充的氧气定义氧空位的浓度。 CIC夹层还包括在强氧化环境中沉积在第一绝缘层上的第二导电层，以便降低第一绝缘层中氧空位的浓度，从而在第一绝缘层之间提供富氧界面层和第二导电层，以便在第二导电层内捕获多个氧原子。富氧界面层和第二导电层用作氧空位吸收器，用于吸收源于第一绝缘层的迁移氧空位，从而降低第一绝缘层中氧空位的浓度，从而减少氧空位的累积接口层。因此，第一绝缘层提供增加的介电常数和增加的电流流过其中，从而增加CIC夹层的电容，并且减少流过CIC夹层的漏电流。

10. 发明申请

US20060292814A1 Methods of forming integrated circuitry 有权
公开(公告)号：US20060292814A1
公开(公告)日：2006-12-28
申请号：US11515432
申请日：2006-08-31
申请人： Cem Basceri , Gurtej Sandhu
发明人： Cem Basceri , Gurtej Sandhu
IPC分类号： H01L21/20
CPC分类号： H01L29/66181 , H01L28/91
摘要： In one implementation, an opening within a capacitor electrode forming layer is formed over a substrate. A spacing layer is deposited over the capacitor electrode forming layer to within the opening over at least upper portions of sidewalls of the opening. The spacing layer is formed to be laterally thicker at an elevationally outer portion within the opening as compared to an elevationally inner portion within the opening. A spacer is formed within the opening by anisotropically etching the spacing layer. The spacer is laterally thicker at an elevationally outer portion within the opening as compared to an elevationally inner portion within the opening. After forming a first capacitor electrode layer laterally over the spacer, at least a portion of the spacer is removed and a capacitor dielectric region and a second capacitor electrode layer are formed over the first capacitor electrode layer.

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