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1. 发明授权

US4825459A Local loop test arrangement in an echo canceller based full duplex modem 失效
标题翻译：基于回波消除器的全双工调制解调器中的本地环路测试布置
公开(公告)号：US4825459A
公开(公告)日：1989-04-25
申请号：US814673
申请日：1985-12-30
申请人： Cecil W. Farrow , William E. Keasler, Jr. , Joseph Maruscsak , David G. Shaw
发明人： Cecil W. Farrow , William E. Keasler, Jr. , Joseph Maruscsak , David G. Shaw
IPC分类号： H04B3/23 , H04L1/24 , H04B17/00
CPC分类号： H04B3/23 , H04L1/24
摘要： In accordance with the present invention, local loop testing in an echo canceller based modem is provided in a manner in which proper operation of both the receiver and echo canceller can be assessed simultaneously. Specifically, the modem includes means for generating data and interfering symbol sequences and for applying the interfering sequence to both the echo canceller and the modem transmitter, while applying the data sequence only to either the transmitter or the echo canceller. During closed loop testing, the modem connection to the transmission line is opened, and a portion of the output of the modem transmitter is applied to the modem receiver via a leakage path through the hybrid. The received symbol is subtracted from the echo canceller output, resulting in application to the receiver of only a version of the data symbol sequence. Advanced knowledge of the characteristics of the data symbol sequence allows proper receiver operation to be verified.
摘要翻译：根据本发明，以可以同时评估接收机和回波消除器两者的适当操作的方式提供基于回波消除器的调制解调器中的本地环路测试。具体地，调制解调器包括用于生成数据和干扰符号序列并用于将干扰序列应用于回波消除器和调制解调器发送器的装置，同时仅将数据序列应用于发射器或回波消除器。在闭环测试期间，与传输线路的调制解调器连接打开，并且调制解调器发射机的输出的一部分经由混合器的泄漏路径被应用于调制解调器接收器。从回波消除器输出中减去接收到的符号，导致只向数据符号序列的版本应用于接收器。对数据符号序列特征的高级知识允许验证适当的接收机操作。

2. 发明授权

US5541961A Digitally controlled high resolution hybrid phase synthesizer 失效
标题翻译：数字控制高分辨率混合相位合成器
公开(公告)号：US5541961A
公开(公告)日：1996-07-30
申请号：US290253
申请日：1994-08-15
申请人： Cecil W. Farrow
发明人： Cecil W. Farrow
IPC分类号： H03K5/13 , H04L7/00
CPC分类号： H03K5/131
摘要： An incremental phase shifter for digital signals adapted to combine weighted amount of two quadrature square waves so as to generate a wave having a phase intermediate the respective phases of the two quadrature square wave signals. The generated wave is then processed in a limiting and integrating circuit so as to produce a square wave which is linearly related to the assigned weighted amounts of the two quadrate square waves.
摘要翻译：一种用于数字信号的增量移相器，适于组合两个正交方波的加权量，以便产生具有两个正交方波信号的相位中间相位的波。然后在限制和积分电路中处理所产生的波，以产生与两个正方形方波的分配的加权量线性相关的方波。

3. 发明授权

US5088057A Rational rate frequency generator 失效
标题翻译：合理的频率发生器
公开(公告)号：US5088057A
公开(公告)日：1992-02-11
申请号：US504812
申请日：1990-04-05
申请人： Daniel Amrany , Cecil W. Farrow
发明人： Daniel Amrany , Cecil W. Farrow
IPC分类号： G06F7/68
CPC分类号： G06F7/68
摘要： A rational rate generator circuit is disclosed where the output signal frequency, f.sub.o, is rationally related to the input signal frequency, f.sub.i, by: f.sub.o =f.sub.i (P/Q). This rational rate generator is capable of a high-resolution output, where the resolution is only limited by the value of the integers P and Q, with P
摘要翻译：公开了一种合理的速率发生器电路，其中输出信号频率fo与输入信号频率fi合理地相关：f 1 = fi（P / Q）。该合理速率发生器能够具有高分辨率输出，其中分辨率仅受P＆Q整数的值的限制，P

4. 发明授权

US4709374A Technique for decision-directed equalizer train/retrain 失效
标题翻译：决策均衡器火车/再训练技术
公开(公告)号：US4709374A
公开(公告)日：1987-11-24
申请号：US628147
申请日：1984-07-05
申请人： Cecil W. Farrow
发明人： Cecil W. Farrow
IPC分类号： H04L27/01 , H03H7/30 , H04B3/04
CPC分类号： H04L27/01
摘要： An adaptive equalizer for data signals is allowed to start up and train in a wholly decision-directed mode but is precluded from converging to an incorrect state by inhibiting equalizer updating for equalizer output values which fall within a predetermined null zone.
摘要翻译：允许用于数据信号的自适应均衡器以完全决策模式启动和训练，但是通过抑制落在预定空区域内的均衡器输出值的均衡器更新来阻止会聚到不正确状态。

5. 发明授权

US4866647A Continuously variable digital delay circuit 失效
标题翻译：连续可变数字延迟电路
公开(公告)号：US4866647A
公开(公告)日：1989-09-12
申请号：US152281
申请日：1988-02-04
申请人： Cecil W. Farrow
发明人： Cecil W. Farrow
IPC分类号： H04L27/00 , G06F17/17 , H03H17/00 , H03H17/06 , H04B14/04
CPC分类号： H03H17/028 , G06F17/17 , H03H17/06
摘要： The process of interpolating between two different sampling rates at any point in a sampling interval is obtained using a transversal filter arranged as a continuously variable digital delay line in which the tap coefficients of the delay line are made to be a function of the coefficients of an nth degree polynomial and the delay between the two sampling rates.

6. 发明授权

US4259648A One-bit frequency-shift-keyed modulator 失效
标题翻译：一位频移键控调制器
公开(公告)号：US4259648A
公开(公告)日：1981-03-31
申请号：US56531
申请日：1979-07-11
申请人： Cecil W. Farrow
发明人： Cecil W. Farrow
IPC分类号： H04L27/12 , H04L27/22
CPC分类号： H04L27/122
摘要： A shift-keyed modulator utilizes a lookup table (41) to provide a binary sequence of digits one at a time. Since the binary digits are selected so that their accumulation represents the amplitudes of a series of points on a theoretical sinusoidal wave, a low-pass filter (51) acting as an integrator is able to provide a sinusoidal wave signal. Furthermore, the low-pass filter includes gates that operate in push-pull fashion to form a balanced configuration for cancelling even ordered harmonic distortion. The modulator has a rate multiplier (11) responsive to space/mark signaling for controlling the rate the the binary digits are produced by the lookup table. A second group of binary digits is stored in the lookup table and is read out concurrently with the first sequence. Alternate pairs of gates (52 and 53 or 54 and 55) are enabled in the low-pass filter to provide binary data signals for either of the frequency bands used in duplex data signaling circuits.
摘要翻译：移位键调制器利用查找表（41）来一次提供一个数字的二进制序列。由于选择二进制数字使得其累加表示理论正弦波上的一系列点的幅度，所以充当积分器的低通滤波器（51）能够提供正弦波信号。此外，低通滤波器包括以推挽方式操作的门，以形成用于消除均匀有序谐波失真的平衡配置。调制器具有响应于空间/标记信令的速率倍增器（11），用于控制由查找表产生的二进制数字的速率。第二组二进制数字存储在查找表中，并与第一个序列同时读出。在低通滤波器中使能交替的门对（52和53或54和55），以为双工数据信号电路中使用的任一个频带提供二进制数据信号。

7. 发明授权

US5163066A Synchronizing the operation of multiple equilizers in a digital communications system 失效
标题翻译：在数字通信系统中同步多个均衡器的操作
公开(公告)号：US5163066A
公开(公告)日：1992-11-10
申请号：US705246
申请日：1991-05-24
申请人： Robert L. Cupo , Cecil W. Farrow
发明人： Robert L. Cupo , Cecil W. Farrow
IPC分类号： H04L7/02 , H04L25/03 , H04L25/14
CPC分类号： H04L7/0029 , H04L25/03038 , H04L25/14 , H04L7/0041
摘要： In a dual-duplex system wherein the communications channels have associated propagation delays which are typically different from one another, equalizers are connected to operate upon the signal received from each channel. To synchronize the operation of these equalizers to each other, the coefficients of each equalizer are updated when the training sequence is received from at least one of the communications channels. The sequence of symbol values in the training sequence may either be known or unknown to the receiver prior to transmission. When this sequence is detected, the coefficient updating circuit for each equalizer operates in response to a common reference signal. This reference signal includes a plurality of symbols and the value of each symbol is supplied at the same time to each equalizer coefficient updating circuit. This technique generates coefficients which compensate for propagation delay differences between the communications channels and is applicable to communications systems wherein data is distributed and transmitted through a plurality of communications channels.
摘要翻译：在双工双工系统中，其中通信信道具有通常彼此不同的相关联的传播延迟，均衡器被连接以对从每个信道接收到的信号进行操作。为了使这些均衡器的操作彼此同步，当从至少一个通信信道接收到训练序列时，更新每个均衡器的系数。在发送之前，训练序列中的符号值的序列可以是接收器的已知或未知的。当检测到该序列时，每个均衡器的系数更新电路响应于公共参考信号而工作。该参考信号包括多个符号，并且每个符号的值同时被提供给每个均衡器系数更新电路。该技术产生补偿通信信道之间的传播延迟差异的系数，并且可应用于通过多个通信信道分发和发送数据的通信系统。

8. 发明授权

US4843581A Digital signal processor architecture 失效
标题翻译：数字信号处理器架构
公开(公告)号：US4843581A
公开(公告)日：1989-06-27
申请号：US48189
申请日：1987-05-11
申请人： Robert L. Cupo , Cecil W. Farrow
发明人： Robert L. Cupo , Cecil W. Farrow
IPC分类号： H03H17/06
CPC分类号： H03H17/06 , H03H2218/08
摘要： The computational processing power of a Digital Signal Processor (DSP) in linear-phase Finite Impulse Response Filter (FIR) applications is essentially doubled by taking advantage of either the even (symmetrical) or odd (antisymmetrical) symmetry of the response of such a filter.
摘要翻译：通过利用这种滤波器的响应的均匀（对称）或奇数（反对称）对称性，线性相有限脉冲响应滤波器（FIR）应用中的数字信号处理器（DSP）的计算处理能力基本上是双倍的。

9. 发明授权

US4815103A Equalizer-based timing recovery 失效
标题翻译：基于均衡器的定时恢复
公开(公告)号：US4815103A
公开(公告)日：1989-03-21
申请号：US113973
申请日：1987-10-29
申请人： Robert L. Cupo , Cecil W. Farrow
发明人： Robert L. Cupo , Cecil W. Farrow
IPC分类号： H04L7/02 , H04L25/03 , H04B3/04
CPC分类号： H04L7/0058 , H04L25/03044
摘要： In a data receiver employing a fractionally spaced equalizer, the phase with which samples of the received signal are formed is controlled in response to a signal indicative of the center of gravity of the equalizer coefficient.
摘要翻译：在采用分数间隔均衡器的数据接收机中，响应于指示均衡器系数的重心的信号来控制形成接收信号的采样的相位。

10. 发明授权

US4594479A Fast start-up of adaptive echo canceler or echo measurement device 失效
标题翻译：快速启动自适应回波消除器或回波测量装置
公开(公告)号：US4594479A
公开(公告)日：1986-06-10
申请号：US524421
申请日：1983-08-18
申请人： Cecil W. Farrow , Jack Salz
发明人： Cecil W. Farrow , Jack Salz
IPC分类号： H04B3/23 , H04B3/20
CPC分类号： H04B3/238
摘要： A method and apparatus for rapid initialization of the transversal filter efficients in an echo canceler or echo measurement device is described. During initialization, a first data sequence is applied to a transmission channel, and an error signal representing the difference between the resulting echo and a replica thereof generated by the transversal filter is formed. The coefficients used to form the replica (in the case of an echo canceler) or to model the transmission channel (in the case of an echo measurement device) are then updated as a function of the error and a second data sequence which is orthogonal to the first sequence.
摘要翻译：描述了用于在回波消除器或回波测量装置中快速初始化横向滤波器系数的方法和装置。在初始化期间，将第一数据序列应用于传输信道，并且形成表示由横向滤波器产生的所得到的回波与其副本之间的差异的误差信号。用于形成副本的系数（在回波消除器的情况下）或对传输信道建模（在回波测量装置的情况下）然后作为误差的函数被更新，并且与第二数据序列正交第一个序列。

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